隨著半導體產業發展，三維堆疊積體電路(3DS-IC)是一項突破莫爾定律的關鍵技術，由矽導微孔(Through-Silicon-Via, TSV)晶圓可作為中介層(Interposer)進行異質元件間的三維堆疊接合。矽導微孔晶圓因具高深寬比特徵，於電鍍填孔後銅膜較厚，本研究延續先前實驗室發展的電致動力輔助化學機械平坦化製程(EKF-CMP)，主要為設計組合式電極，透過電致動力使拋光液產生擾動，提高磨粒使用率及電極重複使用等目標。研究方法先進行流場可視化驗證磨粒擾動情形，建構拋光墊上的反應區計算方法及分析其均勻性之模擬程式。實驗部分使用銅膜晶圓進行兩款拋光墊反應區設計之EKF-CMP製程並與傳統CMP製程比較，結果為新型反應區設計之EKF-CMP的材料移除率可提升24.1%，在TSV晶圓製程參數比較中，發現新型反應區設計之EKF-CMP製程較快達製程終點，且能減少29.7%的銅薄膜凹陷(Dishing)程度。實驗成果可驗證本研究之EKF-CMP製程及組合式電極設計可提升TSV-CMP之材料移除率並降低銅薄膜凹陷。未來研究可針對適用於EKF-CMP之拋光液和拋光墊設計進一步發展。

As rapid development of semiconductor industry, three dimensional stacking integrated circuit (3DS-IC) has been considered to be a critical technology to break through Moore’s Law. For 3DS-IC, the Through–Silicon-Via (TSV) wafer is usually used as an interposer for stacking or integrating heterogeneous element. The high aspect ratio (HAR) of TSV needs higher thickness of copper film by electroplating. This study is to improve the Electrical Kinetic-Force Assisted Chemical Mechanical Planarization (EKF-CMP) process with a modularized conductive plate design to generate electro-osmosis flow of slurry circulation for improving the removal rate of TSV Cu-CMP. The reaction region of polishing pad has been estimated with different pad punching grooving and hole arrangement by developed method and software. A visualization test result can be used for identifying uniformity of reaction region of pad in EKF-CMP. Experimental method of TSV-CMP by two kinds of pad reaction region design and conventional CMP haven been performed and investigated. Results have shown that the new type of EKF-CMP can achieve material removal rate (MRR) up to 24.19% of blanket Cu-CMP as compared with the conventional CMP. For TSV patterned Cu-CMP, dishing can be reduced about 29.7% compared with conventional CMP. Finally, the new EKF-CMP has been verified to improve the MRR and also reducing the dishing of TSV-CMP. Future work can focus on higher MRR with modified slurry and pad design in EKF-CMP.

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