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研究生: 張哲瑋
Che-Wei Chang
論文名稱: 具多模式控制之高效率降壓型轉換器
High Efficiency Buck Converter with Multi-Mode Control
指導教授: 林景源
Jing-Yuan Lin
口試委員: 許益捷
Yi-Chieh Hsu
林景源
Jing-Yuan Lin
邱煌仁
Huang-Jen Chiu
張佑丞
Yu-Chen Chang
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2021
畢業學年度: 109
語文別: 中文
論文頁數: 79
中文關鍵詞: 漣波調變定截止時間控制降壓型轉換器隨輸入電壓變頻隨負載變頻波峰電壓切換
外文關鍵詞: Fixed off-time control, Buck converter, Variable frequency with input voltage, Variable frequency with current, Peak voltage switching
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  • 近年來隨著科技日新月異,可攜式電子產品需求逐漸增加,用來提供電源且具有小體積以及高效能的切換式穩壓器越來越重要。為了使電路達到高效能,因此改善不同負載下的切換頻率,本論文所提出使用漣波調變定截止時間控制(Fixed Off-time Control, FOT)的降壓型轉換器,並加上隨負載變頻以及波峰電壓切換機制來提升轉換效能。一般而言,在傳統的漣波調變定截止時間控制架構,整體的系統頻率皆會隨著輸入電壓上升而上升,此時的切換損耗亦隨著上升。故本論文藉由新型FOT控制使得系統切換頻率隨著輸入電壓上升而下降,藉此大量降低切換損耗。此外,在輕載時轉換效能由切換損所主導,故本論文提出兩種機制分別為隨負載變頻(Variable Frequency with Current, VFC)以及波峰電壓切換(Peak Voltage Switching, PVS)使切換損有效降低;重載時,本論文提出的隨負載變頻機制使電路能有較高的轉換效能。
    本晶片以TSMC T18HVG2製程實現,晶片面積含PADs為1.97×1.71485 mm2。輸入電壓範圍為16 V至32 V以及輸出電壓為12 V,切換頻率434.87kHz至999.9kHz,外接的電感與電容分別為18μH與10μF,輸出負載範圍為60mA至600mA。當負載為60mA至100mA 時,控制模式使用隨負載變頻機制;當負載為100mA至200mA 時,控制模式為雙模式(隨負載變頻以及波峰電壓切換) ;當負載為200mA至600mA 時,控制模式使用隨負載變頻機制。量測顯示最高效率點發生在負載為550mA,效率可達92.64%。


    In recent years, with the rapid of science and technology, the increasing demand of portable products, used to provide power of portable products with small size and high efficiency power converter becomes more and more important. In order to achieve high efficiency of the circuit and therefore improve the switching frequency under different loads, this thesis proposes a buck converter that uses ripple-based modulation fixed off-time(FOT) control, the variable frequency with current(VFC) control and peak voltage switching(PVS) control are added to improve the conversion efficiency.
    Generally speaking, the switching frequency of traditional FOT control increases with the input voltage, and the switching losses also increases with this. Therefore, this thesis uses a new type of FOT control to make the system switching frequency decreases as the input voltage increases, thereby greatly reducing switching losses. In addition, the switching efficiency is dominated by switching losses at light load and therefore this thesis proposes two mechanisms: variable frequency with current(VFC) control and peak voltage switching(PVS) to effectively reduce the switching losses. Under full load, this thesis proposes variable frequency with current(VFC) control enables the circuit to have higher conversion efficiency.
    This chip is realized by TSMC T18HVG2 process. The chip area contains PADs of 1.97×1.71485 mm2. The input voltage range is 16V to 32V and the output voltage is 12V, the switching frequency is 434.87kHz to 999.9kHz , the external inductance and capacitance are 18μH and 10μF, the output load range is 60mA to 600mA. When the load is 60mA to 100mA, the VFC control will turn on, when the load is 100mA to 200mA, the dual mode (VFC and PVS) control will turn on, when the load is 200mA to 600mA the VFC control will turn on. Measurements show that the highest efficiency is 92.64% at output load equal 550mA.

    摘 要 i Abstract ii 致 謝 iv 目 錄 v 圖目錄 vii 表目錄 x 第一章 緒 論 1 1.1研究動機與目的 1 1.2論文大綱 5 第二章 DC-DC降壓型轉換器基本定義原理 6 2.1一般規格 6 2.1.1線調節率 6 2.1.2負載調節率 6 2.1.3暫態響應 7 2.2損耗與效率分析 8 2.2.1開關導通損失 8 2.2.2開關切換損失 9 2.2.3靜態損失 10 2.2.4效率分析 10 第三章 漣波調變定截止時間控制與變頻機制之分析 11 3.1漣波調變定截止時間控制原理與穩定條件 11 3.2漣波調變定截止時間控制之切換頻率變化 14 3.3隨負載變頻機制之分析 16 3.4隨輸入電壓變頻機制之分析 19 第四章 波峰電壓切換機制 20 4.1 波峰電壓切換機制之原理 20 4.2 波峰電壓切換機制之分析 21 第五章 降壓型轉換器設計與實現 25 5.1整體電路簡介 25 5.2子電路設計 27 5.2.1上橋開關電流偵測電路 27 5.2.2新型固定截止時間電路 29 5.2.3波峰電壓切換電路 31 5.2.4隨負載變頻電路(連續導通模式) 32 5.2.5隨負載變頻電路(不連續導通模式) 34 5.2.6電壓位準轉換電路 36 第六章 模擬結果 38 6.1降壓型轉換器之模擬波形 38 6.2模擬結果比較與討論 46 第七章 晶片量測結果 47 7.1晶片佈局圖 47 7.2晶片腳位配置與定義 48 7.3晶片量測結果 51 第八章 結論與未來展望 62 8.1結論 62 8.2未來展望 63 參考文獻 64

    [1] Abraham I. Pressman, Keith Billings, Taylor Morey, Switching Power Supply Design. McGraw-Hill Companies, 2009 3nd.
    [2] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics.Norwell, MA: Kluwer Academic, 2001 2nd.
    [3] Daniel W. Hart, Power Electronics. McGraw-Hill, 2010 1nd.
    [4] R. Redl and J. Sun, “Ripple-based control of switching regulators-An overview,” IEEE Trans. Power Electron., vol. 24, no. 12, pp. 2669-2680, Dec. 2009.
    [5] Rohm semiconductor Application Notes, “Efficiency of Buck Converter : Power Management”Dec. 2016
    [6] B. C. Bao, X. Zhang, J. P. Xu and J. P. Wang, "Critical ESR of output capacitor for stability of fixed off-time controlled buck converter," in Electronics Letters, vol. 49, no. 4, pp. 287-288, 14 Feb. 2013.
    [7] C. Yeh and Y. Lai, "Novel hybrid control technique with constant on/off time control for DC/DC converter to reduce the switching losses," 2009 International Conference on Power Electronics and Drive Systems (PEDS), Taipei, 2009, pp. 848-853.
    [8] C. Yeh, X. Zhao and J. Lai, "An investigation on zero-voltage-switching condition in synchronous-conduction-mode buck converter," 2017 IEEE Energy Conversion Congress and Exposition (ECCE), Cincinnati, OH, 2017, pp. 1728-1732.
    [9] Z. Liu and H. Lee, "A Wide-Input-Range Efficiency-Enhanced Synchronous Integrated LED Driver With Adaptive Resonant Timing Control," in IEEE Journal of Solid-State Circuits, vol. 51, no. 8, pp. 1810-1825, Aug. 2016.

    [10] Natasa Mitrovic, Reinhard Enna and Horst Zimmermann "An Integrated Current Sensing Circuit with Comparator Function for Buck DC-DC Converter in HV-CMOS" in 2016 IEEE International Conference on Electronics, Circuits and Systems(ICECS). 11-14, Dec. 2016.
    [11] C. Y. Leung, P.K.T. Mok, K. N. Leung, and M. Chan, “An integrated CMOS current-sensing circuit for low-voltage current-mode buck regulator,” IEEE Trans. Circuits and Systems II, Express Briefs, vol. 52, no. 7, pp. 394-397, Jul. 2005.
    [12] L. Shi and L. Xu, "Frequency compensation circuit for adaptive on-time control buck regulator," in IET Power Electronics, vol. 7, no. 7, pp. 1805-1809, July 2014.
    [13] C. Huang and C. Chen, "A High-Efficiency Current-Mode Buck Converter With a Power-Loss-Aware Switch-On-Demand Modulation Technique for Multifunction SoCs," in IEEE Transactions on Power Electronics, vol. 31, no. 12, pp. 8303-8316, Dec. 2016.
    [14] Jia-Ming Liu, Chun-Jen Yu, Yeong-Chau Kuo, and Tai-Haur Kuo, " Optimizing the Efficiency of DC-DC Converters with an Analog Variable-Frequency Controller," APCCAS 2008-2008 IEEE Asia Pacific Conference on Circuits and Systems, 30 Nov.-3 Dec.2008
    [15] Roland van Roy,「消除Buck轉換器中的 EMI問題」,立錡科技股份有限公司,2016年1月。
    [16] 詹子增,“雙模式降壓型功率因數修正器之研製",國立臺灣科技大學電機研究所碩士論文,民國一百零三年
    [17] 王信雄,「開關轉換器-控制理論與設計實務 」,立錡科技股份有限公司,2015年
    [18] W. Liou, T. Chen, Y. Kuo, T. Huang and M. Yeh, "A High Efficiency Dual-Mode Buck Converter IC For Portable Applications," 2007 International Conference on Communications, Circuits and Systems, Kokura, 2007, pp. 1011-1015.
    [19] Yu-Kang Lo, Jing-Yuan Lin, Chao-Fu Wang and Chien-Yu Lin, "Analysis and design of a dual-mode flyback converter," 2010 IEEE International Conference on Sustainable Energy Technologies (ICSET), Kandy, 2010, pp. 1-3.
    [20] Meng Jia, Zhuochao Sun, and Liter Siek, "A Novel Zero-Voltage-Detector for Buck Converter in Discontinuous Conduction Mode(DCM), " 2018 IEEE 4th Southern Power Electronics Conference(SPEC), 10-13 Dec.2018

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