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| 研究生： |
白騏睿 Qi-Rui Bai |
|---|---|
| 論文名稱： |
AES 處理器架構之設計與實現 The Design and Implementation of an AES Processor Architecture |
| 指導教授： |
林銘波
Ming-Bo Lin |
| 口試委員: |
林銘波
Ming-Bo Lin 陳郁堂 Yie-Tarng Chen 林昌鴻 Chang-Hong Lin |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
| 論文出版年： | 2019 |
| 畢業學年度： | 107 |
| 語文別： | 中文 |
| 論文頁數： | 60 |
| 中文關鍵詞： | 先進加密標準 、Rijndael 演算法 、即時運算模式 、金鑰擴展單元 、位元組替代轉換 、混合行運算 |
| 外文關鍵詞： | AES, Rijndael algorithm, on-the-fly, key expansion, s-box, mix-column |
| 相關次數： | 點閱：543 下載：0 |
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本論文中提出了一個低成本的 AES 處理器架構，以使用指令的方式，每次處理一筆 128 位元的輸入資料。資料與外部金鑰以每次 32 位元方式依序輸入，外部金鑰可支援 AES 128/192/256 標準。為了更進一步的節省面積，在 AES 演算法的回合運算單元的設計中，提出兩項改善：其ㄧ、在位元組替代轉換模組中，使用唯讀記憶體(ROM)，以有效分配「現場可程式化邏輯閘陣列」(FPGA)的資源；其二、在混合行轉換模組中，將演算法簡化，找出相同的運算，以共享相同的電路。與傳統的 AES 架構比較，提出的AES 處理器架構最大可以節省將近一半的邏輯閘數量。
本論文提出的AES 處理器架構已經在 Xilinx 的 Virtex-5 系列 FPGA (xc5vlx110t)上實現與驗證。它一共消耗了2612個 LUT 與927個暫存器(約為整個FPGA資源的4%)，工作頻率為 71.3 MHz，而資料處理量最高為 52.15 Mbps。
In the thesis, we propose an AES processor architecture, which can handle 128-bit data input each time by executing instructions. The 32-bit input is in the order of the data and then the external key. The external key can support the AES 128/192/256 standard. To further reduce the area of the proposed architecture, the following two improvements are made: First, the composite field arithmetic is carried out with read-only memory (ROM) so as to effectively distribute the hardware resources of the field programmable gate array (FPGA). Second, the mix-column transformation is simplified to find the common operation in order to share the common circuit. The resulting architecture can save about a half area in comparison with the conventional AES architecture.
The proposed and designed AES processor architecture has been implemented and verified with a Xilinx Virtex-5 FPGA device (xc5vlx110t). It needs 2,612 LUTs and 927 registers, about 4% total resource of the FPGA device, operates at 71.3 MHz, and can achieve a throughput of up to 52.15 Mbps.
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[2] AES home page, URL: http://www.nist.gov.aes/.
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[10] M. Y. Wang, C. P. Horng, C. W. Wu and C. T. Huang “Single- and Multi-core Configurable AES Architectures for Flexible Security.” IEEE Trans. on VLSI Systems, Vol. 17, Issue 12, July 21 2009, PP. 546-547.
