Flying-Adder 是一種利用特殊方式產生時脈訊號的數位電路，它擁有著快速
切換的功能，但由於是混和式設計，搭配了類比的鎖相迴路以及數位 Flying-Adder
電路，有著面積較大以及功率消耗高的缺點。本篇論文則提出了利用多工器設計
出新式的數位控制震盪器，來達成全數位化的 Flying-Adder 鎖相迴路。此電路調
整階數少，鎖定時間快，利用 Flying-Adder 架構達成的快速切換頻率能夠在 2 個
週期內能夠完成。相位偵測器部分使用了 Cyclic TDC 以及 Vernier Delay Line 進
行實作，以能夠獲得頻寬範圍較大的相位偵測器，以及減少控制訊號調整時抖動
的程度。
完成的電路使用 TSMC 0.18-um CMOS 1P6M cell-based 製程實現，其核心面
積約為 283 um X 281 um，整體面積為 900 um X 898 um。藉由 NC-Verilog 模擬
後，得到輸出頻率範圍在 390.7 MHz 到 7.53 MHz，以及最大鎖定時間為 20 個週
期。

The flying-adder is a digital circuit that a novel architecture is used to generate a clock signal. Its feature is fast switch. Because of mixed-signal design, combing this structure with an analog voltage control oscillator along with an analog filter will need more area and consume more power as compared to other structures. As a consequence, in this thesis an even-stage all-digital control oscillator based on the multiplexer is used to implement a flying-adder all-digital phase-locked loop. To take the advantages of wider bandwidth and small jitters, the phase detector is designed with the cyclic TDC and a Vernier delay line. The resulting flying-adder-based ADPLL can reduce the chip area, get better power efficiency, and switch rapidly in 2 cycles.
The ADPLL circuit designed is implemented with the TSMC 0.18-um CMOS
1P6M cell-based library. The core area is 283 um x 281 um, and the die area is 900 um x 898 um. With NC-Verilog simulations, the output signal bandwidth is 390.7 MHz, the maximum frequency is 390.7 MHz, and the minimum frequency is 7.53 MHz. The lock time is at most 20 cycles.

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