本論文研究為應用於2.4GHz無線射頻收發器之全數位式鎖相迴路設計，其中數位控制振盪器與控制器為本論文之設計重點，以邏輯閘架構設計出高頻且高解析度的振盪器，突破以往ADPLL僅能操作在幾百MHz的限制，大幅提升了ADPLL的應用與價值，且在DCO當中加入了同步觸發的機制來減少鎖定時間。在控制器的部份，追鎖時將控制碼與Step的位元擴展，可增加鎖定後的穩定性，另外控制器還加入了可調機制，設計者可根據先前的鎖定結果，調整控制碼與Step，在往後的應用中可加快鎖定速度。
具可調機制的高頻、高解析度全數位式鎖相迴路晶片是利用台積電0.18um 1P6M製程來實現，且完全可由Cell-Based設計流程來完成，因此電路具備可攜性，可在不同的製程當中被實現，也縮短了設計時間，操作頻段為1563MHz~1702MHz，LSB解析度可達到0.14ps，最大功率消耗為9.26mW，晶片面積大約為718um*718um。

This thesis presents an all-digital phase-locked loop for 2.4GHz transceiver applications. It focuses on designing digital controlled oscillator and controller. The DCO is completely designed in standard logic gates to achieve GHz frequency and high resolution. Synchronic trigger mechanism is included in the DCO control circuit to reduce the lock time. The controller extends the bit widths of the DCO control code and the step size registers. The control code and the step size can be adjusted according to the previous locking result. Therefore, we can accelerate the lock-in process next time.
The chip is fabricated in TSMC 0.18um 1P6M process. It is designed in Cell-Based design flow. Thus, the circuit has high portability. The operating range of the chip is from 1563MHz to 1702MHz. The LSB resolution is 0.14ps. The maximum power consumption is 9.26mW. The chip area is 718um x 718um.

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