本論文將提出具有頻率偵測及相位頻率誤差補償功能的演算法。首先，我們提出了一個振盪週期對應控制碼呈高線性度的新型數位控制振盪器(DCO)架構。其中頻率偵測的機制是利用計算此數位控制振盪器其最高頻或最低頻經過除頻器後產生的回授訊號Fback和參考頻率Fref間的週期差，以產生數位控制振盪器的預測控制碼。其後的每個參考頻率週期都將進行相位誤差補償機制，抵銷參考頻率Fref和除頻後的輸出頻率Fback間的相差以解決鎖相迴路中常見的相位誤差累積問題。並將相位頻率補償機制應用在全數位式鎖相迴路的追鎖過程。待系統鎖定後再藉由拓展控制碼位元數，以增加鎖定後頻率的穩定性。

本論文的晶片是採用TSMC 0.18 um 1P6M CMOS製程來實現，除了高解析度的數位控制振盪器需要採用Full-custom設計流程完成外，其餘電路完全可由Cell-Based設計流程來完成。系統操作頻段為598 MHz至1.4 GHz，數位控制振盪器的解析度可達0.34 ps ，操作在1.02 GHz下最大功率消耗為28 mW 、晶片面積大約為1.23 mm2 。

This thesis presents a frequency estimation method and a phase-frequency compensation mechanism for an all digital phase-locked loop (ADPLL). First, a novel digital-controlled oscillator (DCO) was designed. This DCO possesses good linear relation between control codes and oscillating period. The frequency estimation method generates the predicted control code by calculating the cycle time difference between the reference clock and the derived feedback signal from the DCO. After that, the phase error compensation mechanism is activated to resolve the problem of phase error accumulation. Next, the phased-frequency compensation mechanism is used in the tracking mode of the ADPLL. On the other hand, after the system is locked, the control code is extended to enhance the frequency stability.
The proposed ADPLL chip was fabricated in TSMC 0.18um 1P6M CMOS process. The DCO is implemented by the full-custom design flow. The other part of the ADPLL is realized by the cell-based design flow. The output frequency range is from 598 MHz to 1.4 GHz with 1-MHz tuning step. The resolution of the DCO is 0.34 ps. The maximum power consumption is 28 mW, and the chip size is 1.23 mm2.

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