鎖相迴路發展至今已有十多年歷史，大量文獻提出完整的架構來改善迴路穩定性、穩定時間、迴路頻寬，類比式鎖相迴路相較於數位式的好處為可實現高操作速度的目標，但抖動與參考頻率干擾高低仍是影響鎖相迴路好壞的關鍵，本論文即提出改善參考頻率干擾的新架構。在另一方面，突發式時脈資料回復電路為鎖相迴路的應用，擺脫傳統架構缺陷，無參考時脈訊號的輸入可降低參考訊號與資料之間的頻率誤差，雖全數位架構導致系統操作頻率有限，但優點為可實現完全模組化。
論文中包含兩大部分，分別為利用三角積分調變器來降低參考頻率干擾之鎖相迴路與全數位化無參考時脈輸入之突發式時脈資料回復電路。首先第一部分鑒於系統操作速度的不斷提升，些微的抖動累積對系統皆會造成劇烈影響，如何有效地降低雜訊則成為論文第一部分的研究主軸。實現方法為利用三角積分調變器輸出特性為亂數資料但仍保持相同責任週期，當系統鎖定後，相位頻率偵測器經由多工器切換至改由觸發三角積分調變器之輸出，來達到均化參考頻率干擾之目標。晶片主體面積為0.62mmx0.74mm，功率消耗為31mW，系統鎖定頻率2.4GHz時所量測之參考頻率干擾為低於-58dBc@20MHz。論文第二部分，早期由鎖相迴路為基礎來實現突發式時脈資料回復電路雖可達到不差的效能，但仍存頻率誤差於鎖相迴路震盪器與閘控震盪器(Gated Oscillator)之間，故論文將傳統鎖相迴路的電路架構與文獻[35]進行改良，系統中採用一組數位閘控數位控制震盪器(Gated Digital Control Oscillator, GDCO)，利用匹配的負載設計所得到的輸出頻率進行頻率與相位校正，頻率部分利用真實單相時脈正反器來實現頻率追鎖，因此可取代需消耗龐大晶片面積之傳統鎖相迴路架構，相位部分利用亞歷山大相位偵測器來提高校正的準確性。

Many works have been reported recently in this field and have already enhanced the electrical performance including jitter, loop stability, settling time, and loop bandwidth. However, the jitter and reference spur become serious problems as the progress of the high-speed communication. Therefore, decreasing the reference spur in the charge pump (CP) or divider of the PLL is the main subject in most of the publications. In the first part of this thesis, this work adopts the characteristics of sigma-delta modulator (SDM), which outputs random data but still maintains the same duty cycle and the multiplexer switches clock signal of phase frequency detector (PFD) to trigger voltage level from SDM’s output after stabilizing the system. The PLL circuit has been fabricated in a 0.18um CMOS technology and the core area is 0.62mmx0.72mm. The power consumption is 31mW from a 1.8V supply and the measured reference spur is lower than -58dBc while reference clock input is 20MHz.
In second part of this thesis, an all-digital reference-free burst-mode clock/data recovery (CDR) has been presented. Although a conventional PLL-based burst-mode CDR has good performance, it still has drawbacks of large chip area occupied by the PLL and the frequency error between PLL’s oscillator and matched gated oscillator. The ultimate goal of this thesis is designing a suitable loading of gated digital control oscillator (GDCO) as well as using oscillator’s frequency output (CK1 and CK2) to calibration frequency and phase, in addition, applying edge detector (ED) to accomplish reference-free and solve the problem of the asynchronous clock.

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