本篇論文研究嘗試了一種多相位次取樣鎖相迴路。為了降低抖動，鎖相迴路使用次取樣技術來產生低抖動性能的8相位輸出，並以此架構來滿足多通道類比數位轉換器之應用，其輸出頻率範圍為300MHz至500MHz。另外，為了量測方便，此鎖相迴路僅有一相位的輸出有經過噪聲消除電路，本篇論文另外實現了一個延遲鎖相迴路，以應用在先進製程之超高速多通道類比數位轉換器。本篇論文的第一個晶片實現使用0.18微米CMOS製程，第二個晶片使用28奈米CMOS製程。
第一個晶片是使用次取樣鎖相迴路架構。此晶片使用1.8V電源電壓，在500MHz時，功率消耗為30毫瓦，核心電路之面積為0.1平方毫米。在鎖相迴路輸出頻率為480 MHz時，後模擬值的均方根值抖動約為11.8ps，但量測的均方根值抖動約為193ps。第二個設計改使用延遲鎖相迴路，以應付在28奈米CMOS製程，只有1V電源電壓的情況下，所帶來的設計困難。晶片使用1V電源電壓，在5GHz時，功率消耗為4.2毫瓦，核心電路之面積為0.0043毫米。在DLL輸出頻率為5GHz時，後模擬值的均方根值抖動約為287fs。

In this paper, a multi-phase sub-sampling phase-locked loop is developed. In order to reduce jitter, the phase-locked loop uses sub-sampling technology to generate 8-phase output with low jitter performance, to meets the application of multi-channel analog-to-digital converters with an output frequency range of 300MHz to 500MHz. In addition, for the convenience of measurement, only one phase of the phase-locked loop output passes through the noise cancellation circuit. This paper also implements a delay-locked loop to apply to the ultra-high-speed multi-channel analog-to-digital converter in advanced manufacturing process. The first chip implementation of this paper uses a 0.18-micron CMOS process, and the second chip uses a 28-nm CMOS process.
The first chip uses a subsampled PLL architecture. This chip uses a 1.8V power supply voltage, and at 500MHz, the power consumption is 30mW, and the area of the core circuit is 0.1mm^2. When the PLL output frequency is 480 MHz, the RMS jitter of the post-sim value is about 11.8ps, but the measured RMS jitter is about 193ps. The second design uses a delay-locked loop to cope with the design difficulties caused by a 1V supply voltage in a 28nm CMOS process. The chip uses a 1V power supply voltage. At 5GHz, the power consumption is 4.2mW, and the area of the core circuit is 0.0043mm^2. The post-layout simulation results show that the RMS jitter of DLL is about 287fs.

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