研究生: |
曾福祥 Fu-Hsiang Tseng |
---|---|
論文名稱: |
具新型相位及頻率補償之全數位式鎖相迴路 An All Digital Phase-Locked Loop with Novel Phase and Frequency Error Compensation |
指導教授: |
姚嘉瑜
Chia-Yu Yao |
口試委員: |
陳筱青
Hsiao-Chin Chen 彭盛裕 Sheng-Yu Peng |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電機工程系 Department of Electrical Engineering |
論文出版年: | 2014 |
畢業學年度: | 102 |
語文別: | 中文 |
論文頁數: | 84 |
中文關鍵詞: | 全數位式鎖相迴路 、相位誤差補償 、頻率誤差補償 、數位控制振盪器 |
外文關鍵詞: | all-digital phase-locked loop, phase error compensation, frequency error compensation, digitally controlled oscillator |
相關次數: | 點閱:417 下載:1 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
本論文提出利用新型相位及頻率誤差補償演算法的全數位式鎖相迴路。首先,我們提出了一個振盪週期對應控制碼呈高解析度的新型數位控制振盪器(DCO)架構,此架構之振盪週期與控制碼關係曲線有8條,系統啟動時由粗調頻率選擇器選擇目標頻率所在的曲線。
相位誤差補償機制,是利用計數參考訊號Fref正緣與經除頻器除頻之後產生的回授訊號Fback正緣間的數位控制振盪器週期數,藉此修正除頻器除數,以抵銷Fref和Fback間的相差,先解決鎖相迴路追鎖頻率時的相位誤差累積問題,而其後每個Fref週期都同時進行頻率誤差與相位誤差補償的機制。
頻率誤差補償的機制是由相位誤差補償機制拓展出來,一開始利用數位控制振盪器振盪在選定曲線之中間頻段,並計數Fback正緣和Fref正緣間的DCO訊號週期差,以計算控制碼的改變量(∆Code),達到校正頻率的功能。
相位頻率誤差補償機制應用在全數位式鎖相迴路的追鎖過程。待系統鎖定後再藉由拓展控制碼位元數,以增加鎖定後頻率的穩定性。
本論文的晶片是採用TSMC 0.18 um 1P6M CMOS製程來實現,除了高解析度的數位控制振盪器需要採用Full-custom設計流程完成外,其餘電路完全可由Cell-Based設計流程來完成。DCO操作頻段為598 MHz至1.4 GHz,而其解析度在TT 27℃時介於0.315 ps ~ 0.364 ps。系統操作在960 MHz下功率消耗為4.75 mW 、晶片面積大約為0.88 mm2 。
This thesis presents a phase-frequency error compensation mechanism for an all digital phase-locked loop (ADPLL). First, a novel digital-controlled oscillator (DCO) was designed. This DCO possesses 8 period vs. control code transfer curves with good linearity. When the system starts, the coarse frequency selector selects a proper DCO curve to which the desired frequency belongs.
The phase error compensation mechanism changes the divisor of the divider to resolve the problem of phase error accumulation by calculating the cycle time difference between the positive edge of the reference clock and the positive edge of the feedback signal from the DCO. After that, The frequency error compensation mechanism is activated to generate the correcting amount of the control-code to fix the frequency error. Next, the phased-frequency error compensation mechanism is used in the acquisition mode of the ADPLL. In the tracking mode, after the system is locked, the control code is extended to enhance the frequency stability.
The proposed ADPLL chip was fabricated in TSMC 0.18um 1P6M CMOS process. The DCO was implemented by the full-custom design flow. The other part of the ADPLL is realized by the cell-based design flow. The DCO’s output frequency range is from 598 MHz to 1.4 GHz and its resolution is between 0.315 ps and 0.364 ps at TT 27℃. The power consumption at 960 MHz frequency is 4.75 mW, and the chip size is around 0.88 mm2.
[1] Chia-Tsun Wu, Wen-Chung Shen, Wei Wang, and An-Yeu Wu, “A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 57, no. 6, June 2010.
[2] T. Watanabe and S. Yamauchi, “An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time,” IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 198–204, Feb. 2003.
[3] D. Sheng, C.-C. Chung, C.-Y. Lee, “An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 54, pp. 954 – 958, 2007.
[4] P.-L. Chen, C.-C. Chung, and C.-Y. Lee, “A portable digitally controlled oscillator using novel varactors,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 52, pp. 233–237, May 2005.
[5] D. Sheng, C.-C. Chung, and C.-Y. Lee, “An all-digital phase-locked loop with high-resolution for SoC applications,” IEEE VLSI D.A.T., pp. 207–210, Apr. 2006.
[6] Hua Geng, Dewei Xu, and Bin Wu, “A Novel Hardware-Based All-Digital Phase-Locked Loop Applied to Grid-Connected Power Converters,” IEEE Trans. on Industrial Electronics, vol. 58, no. 5, May 2011.
[7] T.-Y. Hsu, C.-C. Wang, and C.-Y. Lee, “Design and analysis of portable high-speed clock generator,” IEEE Trans. Circuits Syst. II, Analog Digit.Signal Process., vol. 48, no. 4, pp. 367–375, Apr. 2001.
[8] K.-J. Lee, S.-H. Jung, Y.-J. Kim, C. Kim, S. Kim, U.-R. Cho, C.-G. Kwak, and H.-G. Byun, “A digitally controlled oscillator for low jitter all digital phase locked loops,” in Proc. IEEE Asian Solid-State Circuit Conf., pp. 365–368, Nov. 2005.
[9] P.-L. Chen, C.-C. Chung, J.-N. Yang, and C.-Y. Lee, “A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications,” IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1275-1285, Jun. 2006.
[10] Kuo-Hsing Cheng, Kai-Wei Hong, Chi-Hsiang Chen, and Jen-Chieh Liu, “A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 7, July 2011.
[11] K .-H. Choi, J.-B. Shin, J.-Y. Sim, and H.-J. Pard, “An interpolation digitally controlled oscillator for a wide-range all-digital PLL,” IEEE Trans.Circuits Syst. I, Reg. Papers, vol. 56, no. 9, pp. 2055–2063, Sep. 2009.
[12] C.-C. Wang, A digital frequency synthesizer HDL generator for SOC design. National Chiao-Tung University, M.S. Thesis, 2000.
[13] R.-E. Best, Phase Locked Loops: Design, Simulation, and Application. 3rd Edition. Singapore McGraw-Hill Inc., 1993.
[14] 廖煥森, Low-Power Phase-Locked Loop Design. M.S. Thesis, Tamkung University, 1999.
[15] C.-C. Cheng, The analysis and design of all digital phase-locked loop(ADPLL). National Chiao-Tung University, M.S. Thesis, 2001.
[16] A. Zolfaghari and B. Razavi, “A low-power 2.4-GHz transmitter/receiver CMOS IC ,” IEEE J. Solid-State Circuits, vol. 38, pp. 176-183, 2003.
[17] 劉大維, 新型全數位式鎖相迴路之設計. 碩士論文, 淡江大學, 2002.
[18] 高曜煌, 射頻鎖相迴路IC設計. 滄海書局, 2005.
[19] 劉深淵, 楊清淵, 鎖相迴路. 滄海書局, 2006.