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研究生: 曾福祥
Fu-Hsiang Tseng
論文名稱: 具新型相位及頻率補償之全數位式鎖相迴路
An All Digital Phase-Locked Loop with Novel Phase and Frequency Error Compensation
指導教授: 姚嘉瑜
Chia-Yu Yao
口試委員: 陳筱青
Hsiao-Chin Chen
彭盛裕
Sheng-Yu Peng
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2014
畢業學年度: 102
語文別: 中文
論文頁數: 84
中文關鍵詞: 全數位式鎖相迴路相位誤差補償頻率誤差補償數位控制振盪器
外文關鍵詞: all-digital phase-locked loop, phase error compensation, frequency error compensation, digitally controlled oscillator
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  • 本論文提出利用新型相位及頻率誤差補償演算法的全數位式鎖相迴路。首先,我們提出了一個振盪週期對應控制碼呈高解析度的新型數位控制振盪器(DCO)架構,此架構之振盪週期與控制碼關係曲線有8條,系統啟動時由粗調頻率選擇器選擇目標頻率所在的曲線。
    相位誤差補償機制,是利用計數參考訊號Fref正緣與經除頻器除頻之後產生的回授訊號Fback正緣間的數位控制振盪器週期數,藉此修正除頻器除數,以抵銷Fref和Fback間的相差,先解決鎖相迴路追鎖頻率時的相位誤差累積問題,而其後每個Fref週期都同時進行頻率誤差與相位誤差補償的機制。
    頻率誤差補償的機制是由相位誤差補償機制拓展出來,一開始利用數位控制振盪器振盪在選定曲線之中間頻段,並計數Fback正緣和Fref正緣間的DCO訊號週期差,以計算控制碼的改變量(∆Code),達到校正頻率的功能。
    相位頻率誤差補償機制應用在全數位式鎖相迴路的追鎖過程。待系統鎖定後再藉由拓展控制碼位元數,以增加鎖定後頻率的穩定性。
    本論文的晶片是採用TSMC 0.18 um 1P6M CMOS製程來實現,除了高解析度的數位控制振盪器需要採用Full-custom設計流程完成外,其餘電路完全可由Cell-Based設計流程來完成。DCO操作頻段為598 MHz至1.4 GHz,而其解析度在TT 27℃時介於0.315 ps ~ 0.364 ps。系統操作在960 MHz下功率消耗為4.75 mW 、晶片面積大約為0.88 mm2 。


    This thesis presents a phase-frequency error compensation mechanism for an all digital phase-locked loop (ADPLL). First, a novel digital-controlled oscillator (DCO) was designed. This DCO possesses 8 period vs. control code transfer curves with good linearity. When the system starts, the coarse frequency selector selects a proper DCO curve to which the desired frequency belongs.
    The phase error compensation mechanism changes the divisor of the divider to resolve the problem of phase error accumulation by calculating the cycle time difference between the positive edge of the reference clock and the positive edge of the feedback signal from the DCO. After that, The frequency error compensation mechanism is activated to generate the correcting amount of the control-code to fix the frequency error. Next, the phased-frequency error compensation mechanism is used in the acquisition mode of the ADPLL. In the tracking mode, after the system is locked, the control code is extended to enhance the frequency stability.
    The proposed ADPLL chip was fabricated in TSMC 0.18um 1P6M CMOS process. The DCO was implemented by the full-custom design flow. The other part of the ADPLL is realized by the cell-based design flow. The DCO’s output frequency range is from 598 MHz to 1.4 GHz and its resolution is between 0.315 ps and 0.364 ps at TT 27℃. The power consumption at 960 MHz frequency is 4.75 mW, and the chip size is around 0.88 mm2.

    摘要 I Abstract II 誌謝 III 目錄 IV 圖目錄 VII 表目錄 XI 第一章 緒論 1 1-1 研究動機 1 1-2 論文規劃 3 第二章 鎖相迴路介紹與系統應用 4 2-1 類比式鎖相迴路 4 2-2 電荷幫浦式鎖相迴路 5 2-3 全數位式鎖相迴路 6 2-4 系統應用 8 第三章 具相位及頻率誤差補償之數位式鎖相迴路系統架構介紹與模擬 9 3-1 數位控制振盪器 9 3-1.1 數位控制振盪器電路架構 10 3-1.2 後模擬結果 12 3-2 系統架構 16 3-3 時序控制器 19 3-4 粗調頻率選擇器 21 3-5 除頻器 24 3-5.1 除頻器架構 24 3-5.2 雙模數Prescaler 26 3-6 相位頻率偵測器 27 3-7 相位頻率誤差補償器 29 3-7.1 相位誤差累積問題 29 3-7.2 相位誤差補償機制 31 3-7.3 頻率誤差補償機制 33 3-7.4 相位頻率誤差補償器電路架構 36 3-8 細調控制器 37 3-9 演算法運作範例 40 3-10 系統前模擬結果 43 3-11 系統後模擬結果 48 第四章 晶片佈局與量測 50 4-1 設計流程 50 4-2 晶片佈局規劃 51 4-3 量測環境 52 4-4 量測結果 54 4-4.1 Jitter performance之量測結果 54 4-4.2 Clock period jitter之量測結果 56 4-4.3 Cycle-to-Cycle jitter之量測結果 58 4-4.4 Time Interval Error (TIE) 之量測結果 61 4-4.5 鎖定過程控制碼之量測結果 63 4-4.6 頻譜之量測結果 66 4-5 晶片規格列表與文獻比較 68 第五章 結論與未來展望 71 5-1 結論 71 5-2 未來展望 71 參 考 文 獻 72

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