近年來鎖相迴路（Phase-Locked Loops）已廣泛應用於各種電腦工業、通訊電子產品及消費性電子產品，諸如頻率合成器（Frequency Synthesizer）、資料/時脈回復電路（Data/Clock Recovery）及時脈歪斜消除電路（Clock De-skew）等各種與時脈信號息息相關的場合中扮演著不可或缺的角色。本論文提出一個有別於傳統類比式設計代之以全數位的方式建構鎖相迴路的方法，我們稱之為全數位式鎖相迴路（All Digital Phase-Locked Loops, ADPLL），以確保在日益複雜的系統晶片設計上，能提供使用者一個可靠穩健的鎖相迴路智財，加快設計時程與研發效率。
在電路設計中採用一個與以往全然不同觀念的時間至數位轉換器（Time to Digital Converter, TDC），藉由將輸入信號不斷的「縮小」以獲得其正確的時脈週期，免去傳統上需採用快速高頻的取樣電路與寬位元的計數器，達到功率與面積上的改善。另外我們也提出了一個新的細調時間單元（Fine Tuning Unit, FTU）設計方式，藉由三態閘並聯不同數目的反相器，可提供不同位元數的細調頻率解析度。最後晶片的實現上完全採用以硬體描述語言Verilog HDL完成所有電路結構並使用TSMC 0.18 μm CMOS 1P6M標準元件庫設計流程，晶片核心面積為0.25 × 0.25 mm2完成面積為0.75 × 0.75 mm2，可操作頻率由98 MHz至775 MHz，最大功率消耗為80 mW。

Nowadays, PLLs (Phase-Locked Loops) have been widely used in computer industry, communication products, and consumer electronics. They play important roles in clocking circuits such as frequency synthesizer, data/clock recovery, and clock de-skew circuit. We proposed an all digital way so called ADPLL (All Digital Phase-Locked Loop) to construct a solid and reliable IP for phase-locked loops. It can be ensure that the design cycle and productivity will be grow up as the difficulty of SoC design goes wildly.
We provide a totally different concept about TDC (Time to Digital Converter). In contrast to traditional high frequency sampling clock and wide-bit binary counters, the input clock is “shrunk” instead of being counted. Also, we use a set of superinverters to build a new FTU (Fine Tuning Unit) with each constructed by tri-state buffers connected in parallel. It can achieve different DCO fine tune resolutions by the chosen bits. Finally, the whole chip has been implemented by Verilog HDL (Hardware Description Language) in TSMC 0.18μm CMOS 1P6M standard cell based library. The area of this chip is 0.75 × 0.75 mm2 and the output frequency can achieve from 98 MHz to 775 MHz. The maximum power consumption is 80 mW.

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