這篇論文提出一個利用Verilog 和 FPGA 實現了Delta-Sigma Modulator 所架構出的 MASH 1-1-1 的數位電路。此數位電路是專門提供給 PLL 使用的。所搭配的 是一個輸出為 10GHz 的 PLL。
數位電路的組成架構包括累加器、全加器、半加器跟暫存器。如何由數學 Model 轉化成為一個可以實際運作的電路，是此論文中數位電路的重點。另一個重點則是對 PLL 的瞭解。
在設計的程序中包括了設計及模擬。由Verilog 來架構出數位電路，再藉由Xilin 及 Modelsim 等軟體來驗證其實際的運作結果。Simulink 是一個重要的關卡，它能讓控制訊號，及時地，傳送到FPGA電路。
論文最後，是 FPGA 實現了 MASH 1-1-1 的成果。藉由 Verilog 非常方便改變的特性，來達到所想要的 MASH 1-1-1。這是本論文中設計的特點。

Fractional-N synthesizers have many advantages over their conventional counterparts, integer N synthesizers. These include, among others, high frequency resolution, fast channel switching speed, low in-band phase noise, less stringent phase noise requirement on the external VCOs, permitting direct digital modulation.
One way of achieving non-integer multiplication of the reference frequency is through switching the division ration of the divider among different integers so that the “average” divider output cycle seen by the phase frequency detector is a non-integer multiple of the VCO period. However, the dithering of the rising edge of the divider output, as a result of witch action, could cause unacceptably high phase noise and sidebands within the loop bandwidth if a simple bit stream generator is employed. High order Delta-Sigma Modulators capable of shifting low frequency noise into high frequencies are required. The shifted low frequency noise will be subsequently filtered out by the low pass response of the loop.
In this thesis, a digital pipelined third-order MASH Delta-Sigma Modulators (DSMs) is analyzed, designed and implemented on field programmable gate array (FPGA) customer board (Lyrtech). The fractional division causes spurious tones at fractional multiples of the reference frequency. The Delta-Sigma fractional-N architecture seems to be widely accepted the spurious problem as the best one. Xilinx, Matlab, Modemsim and SignaWAVE are software tools for design and implementation. The DSMs are successfully implemented by FPGA. Both simulated and measured results are presented and compared discussed.

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