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研究生: 鍾玉壽
Yi-Su Chung
論文名稱: 以現場可程式化閘陣列實現鎖相迴路延遲矩陣為基礎之高精度時間至數位轉換器
A High Accuracy FPGA Vernier Time-to-Digital Converter Based on PLL Delay Matrix
指導教授: 陳伯奇
Poki Chen
口試委員: 黃育賢
Yuh-Shyan Hwang
陳建中
Jiann-Jong Chen
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2016
畢業學年度: 104
語文別: 中文
論文頁數: 110
中文關鍵詞: 時間至數位轉換電路現場可程式化閘陣列鎖相迴路二維游標延遲矩陣PVT變異抗性
外文關鍵詞: Time-to-Digital Converter(TDC), Field Programmable Gate Array (FPGA), Phase-Locked Loop(PLL), 2-D Vernier, Delay Matrix, PVT-insensitive.
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  • 本論文提出一個實現於現場可程式化閘陣列(Field Programmable Gate Array,FPGA)並利用鎖相迴路延遲矩陣為基礎之時間至數位轉換電路(Time-to-Digital converter,TDC)。過往以二維游標法為基礎的FPGA TDC被提出以實現2.5 ps的解析度和-2.98〜3.23 LSB之積分非線性(INL)誤差[1],但是此方法不能讓所有延遲級的延遲時間完全受到控制,並且TDC的性能與延遲時間的隨機分佈強烈相關。此外,可量測之輸入範圍被限制在20ns以內。所以,本論文改而使用PLL構建二維延遲矩陣來俾便實現一個高準確度、以二維游標法為基礎的FPGA TDC。
    本論文之FPGA TDC不但可以抵抗PVT變異,並且可以達到高解析度與寬廣的量測時間範圍。經過FPGA內建的鎖相迴路構建主PLL與次PLL以提供多個不同的時脈相位,讓所有時脈之相位均勻分佈在0~360度之參考週期內,達到1ps且不受PVT變異影響的解析度,另外並加入偏移校準技術更進一步降低PVT變異對偏移量的影響,並且將輸出偏移誤差抑制在5個LSB之內。長線量測之積分非線性誤差(INL)為-2.471 ~ 2.578 LSB、差分非線性誤差(DNL)為-2.969 ~ 2.813 LSB。並完整測試涵蓋0C到50C的運作功能,成功驗證本時間至數位轉換電路抑制溫度變異之優異效果,整體效能甚至優於大部分的全客戶(Full Custom)設計競爭對手。


    A high accuracy FPGA Vernier time-to-digital converter based on PLL delay matrix is presented. Previously, a FPGA Vernier TDC was proposed to achieve 2.5 ps bin size and -2.98~ 3.23 LSB integral nonlinearity (INL) [1]. However, the cell delays of the delay lines cannot be fully controlled and thus the TDC performance is strongly dependent on the stochastic distribution of the cell delays. Moreover, the input range is limited to be less than 20ns. In this thesis, a high accuracy FPGA Vernier time-to-digital converter (TDC) is realized with PLL delay matrix instead to get rid of the impact of possible PVT variations.
    The proposed TDC is aimed to provide a PVT-insensitive solution with both high resolution and wide measurement range. The delay of all cells is under the precise control of major and minor PLLs. Utilizing the concept of delay wrapping, the PLL phases are distributed evenly within the reference period to achieve an extremely fine resolution. To reduce the impact of temperature-sensitive offset, a cancellation circuit is adopted to substantially reduce the offset and confine the output difference to within merely 5 LSB. Experimental results achieve a PVT-insensitive TDC resolution of 1ps. The long-term integral nonlinearity (INL) is measured to be merely -2.471 ~ 2.578 LSB and the corresponding differential nonlinearity (DNL) is -2.969 ~ 2.813 LSB. This TDC was tested to be fully functional over 0C to 50C ambient temperature range with very low resolution variation. Its performance is even superior to many full-custom TDC designs.

    圖目錄 VII 表目錄 XI 第一章 1 序 論 1 1-1 研究動機 1 1-2 章節介紹 2 第二章 3 時間至數位轉換電路 3 2-1 時間至數位轉換電路簡介 3 2-2 時間至數位轉換電路之架構介紹與說明 7 2-2.1計數器法之時間至數位轉換電路 7 2-2.2抽頭延遲線式之時間至數位轉換電路 11 2-2.3鏈結構延遲線之時間至數位轉換電路 13 2-2.4合併延遲鏈之時間至數位轉換電路 16 2-2.5延遲迴繞法搭配相位排序法之高精度時間至數位轉換電路 18 2-2.6以鎖相迴路為基礎之時間至數位轉換電路 23 2-2.7數位校準 26 2-2.8總結 29 第三章 30 鎖相迴路延遲矩陣為基礎之高精度時間至數位轉換電路 30 3-1 FPGA晶片與本論文所使用的FPGA開發板簡介 30 3-2 鎖相迴路延遲矩陣為基礎之高精度時間至數位轉換電路 32 3-2.1 內嵌於FPGA晶片內的鎖相迴路簡介 34 3-2.2 二維延遲矩陣 36 3-2.3 時間至脈衝產生器 43 3-2.4 同步器(Synchronizer) 45 3-2.5 計數器 47 3-2.6 加總取值電路(Summer) 56 3-2.7 偏移消除電路(Offset Cancelation Circuit) 58 第四章 62 FPGA之時脈網路 62 4-1 時脈偏移問題與時脈樹 62 4-2 Altera Stratix IV系列的時脈網路(Clock Network) 64 第五章 66 實驗量測結果與未來展望 66 5-1 量測儀器簡介 66 5-2 量測環境的建立 70 5-3 量測結果 71 5-3.1 短線量測(Short Term Measurement) 71 5-3.2 中線量測(Mid Term Measurement) 76 5-3.3 長線測量(Long Term Measurement) 80 5-3.4 方均根誤差(RMS Resolution)測量 84 5-3.5 溫度變異測量(Temperature Variation) 85 5-4結論與未來展望 91 參考文獻 92

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