研究生: |
鍾玉壽 Yi-Su Chung |
---|---|
論文名稱: |
以現場可程式化閘陣列實現鎖相迴路延遲矩陣為基礎之高精度時間至數位轉換器 A High Accuracy FPGA Vernier Time-to-Digital Converter Based on PLL Delay Matrix |
指導教授: |
陳伯奇
Poki Chen |
口試委員: |
黃育賢
Yuh-Shyan Hwang 陳建中 Jiann-Jong Chen |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2016 |
畢業學年度: | 104 |
語文別: | 中文 |
論文頁數: | 110 |
中文關鍵詞: | 時間至數位轉換電路 、現場可程式化閘陣列 、鎖相迴路 、二維游標 、延遲矩陣 、PVT變異抗性 |
外文關鍵詞: | Time-to-Digital Converter(TDC), Field Programmable Gate Array (FPGA), Phase-Locked Loop(PLL), 2-D Vernier, Delay Matrix, PVT-insensitive. |
相關次數: | 點閱:415 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
本論文提出一個實現於現場可程式化閘陣列(Field Programmable Gate Array,FPGA)並利用鎖相迴路延遲矩陣為基礎之時間至數位轉換電路(Time-to-Digital converter,TDC)。過往以二維游標法為基礎的FPGA TDC被提出以實現2.5 ps的解析度和-2.98〜3.23 LSB之積分非線性(INL)誤差[1],但是此方法不能讓所有延遲級的延遲時間完全受到控制,並且TDC的性能與延遲時間的隨機分佈強烈相關。此外,可量測之輸入範圍被限制在20ns以內。所以,本論文改而使用PLL構建二維延遲矩陣來俾便實現一個高準確度、以二維游標法為基礎的FPGA TDC。
本論文之FPGA TDC不但可以抵抗PVT變異,並且可以達到高解析度與寬廣的量測時間範圍。經過FPGA內建的鎖相迴路構建主PLL與次PLL以提供多個不同的時脈相位,讓所有時脈之相位均勻分佈在0~360度之參考週期內,達到1ps且不受PVT變異影響的解析度,另外並加入偏移校準技術更進一步降低PVT變異對偏移量的影響,並且將輸出偏移誤差抑制在5個LSB之內。長線量測之積分非線性誤差(INL)為-2.471 ~ 2.578 LSB、差分非線性誤差(DNL)為-2.969 ~ 2.813 LSB。並完整測試涵蓋0C到50C的運作功能,成功驗證本時間至數位轉換電路抑制溫度變異之優異效果,整體效能甚至優於大部分的全客戶(Full Custom)設計競爭對手。
A high accuracy FPGA Vernier time-to-digital converter based on PLL delay matrix is presented. Previously, a FPGA Vernier TDC was proposed to achieve 2.5 ps bin size and -2.98~ 3.23 LSB integral nonlinearity (INL) [1]. However, the cell delays of the delay lines cannot be fully controlled and thus the TDC performance is strongly dependent on the stochastic distribution of the cell delays. Moreover, the input range is limited to be less than 20ns. In this thesis, a high accuracy FPGA Vernier time-to-digital converter (TDC) is realized with PLL delay matrix instead to get rid of the impact of possible PVT variations.
The proposed TDC is aimed to provide a PVT-insensitive solution with both high resolution and wide measurement range. The delay of all cells is under the precise control of major and minor PLLs. Utilizing the concept of delay wrapping, the PLL phases are distributed evenly within the reference period to achieve an extremely fine resolution. To reduce the impact of temperature-sensitive offset, a cancellation circuit is adopted to substantially reduce the offset and confine the output difference to within merely 5 LSB. Experimental results achieve a PVT-insensitive TDC resolution of 1ps. The long-term integral nonlinearity (INL) is measured to be merely -2.471 ~ 2.578 LSB and the corresponding differential nonlinearity (DNL) is -2.969 ~ 2.813 LSB. This TDC was tested to be fully functional over 0C to 50C ambient temperature range with very low resolution variation. Its performance is even superior to many full-custom TDC designs.
[1] Poki Chen, Ya-Yun Hsiao, Yi-Su Chung, Wei Xiang Tsai and Jhih-Min Lin, “A 2.5 ps Bin Size and 6.7 ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging,” IEEE Trans. VLSI Syst., accepted.
[2] A. S. Yousif and J. W. Haslett , “A fine resolution TDC architecture for next generation PET imaging,” IEEE Trans. Nucl. Sci., vol. 54, no. 5, pp. 1574-1582, Oct. 2007.
[3] W. W. Moses, S. Buckley, C. Vu, Q. Peng, N. Pavlov, W. Choong, J. Wu, and C.Jackson, “OpenPET: A flexible electronics system for radiotracer imaging,” IEEE Trans. Nucl. Sci., vol. 57, no. 5, pp. 2532–2537, Oct.2010.
[4] G. Sportelli, N. Belcari, P. Guerra, F. Spinella, G. Franchi, F. Attanasi, S. Moehrs, V. Rosso, A. Santos, and A. Del Guerra, “Reprogrammable acquisition architecture for dedicated positron emission tomography,” IEEE Trans. Nucl. Sci., vol. 58, no. 3, pp. 695–702, Jun. 2011
[5] T. Otsuji, “A picosecond-accurary,700-MHz range si-bipolar time interval counter LSI,” IEEE J. Solid-State Circuit, vol. 28, pp. 941-947, Sept. 1993.
[6] K. Ealgoo, L. Hansang, L. Taeyon, C. Dongbum, and P. Jaehong, “Time of flight (TOF) measurement of adjacent pulses,” in IEEE Nucl. Sci. Symp. Conf. Rec., Nov. 2001, vol. 1, pp. 609–612.
[7] K. Maatta and J. Kostamovaara, “A high-precision time-to-digital converter for pulsed time-of-flight laser radar applications,” IEEE Trans. Instrum. Meas., vol. 47, no. 2, pp. 521–536, Apr. 1998.
[8] N. Paschalidis et al., “A time-of-flight system on a chip suitable for space instrumentation”, in IEEE Nucl. Sci. Symp. Conf. Rec., Nov. 2001, vol. 2, pp. 750–754.
[9] P. Palojarvi, K. Maatta, and J. Kostamovaara, “Integrated time-of-flight laser radar,” IEEE Trans. Instrum. Meas., vol. 46, no. 4, pp. 996–999, Aug. 1997.
[10] H. Brockhaus and A. Glasmachers, “Single particle detector system for high resolution time measurements,” IEEE Trans. Nucl. Sci., vol. 39, no. 4, pp. 707–711, Aug. 1992.
[11] H. Chan and G. W. Roberts, “A jitter characterization system using a component-invariant Vernier delay line,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 1, pp. 79–95, Jan. 2004.
[12] P. Napolitano, A. Moschitta, and P. Carbone, “A survey on time interval measurement techniques and testing methods,” in Proceedings of IEEE Instrumentation and Measurement Technology Conference, pp. 181–186, 2010.
[13] “IEEE standard for terminology and test methods for analog-to-digital converters,” IEEE Std., 13 Jun. 2001.
[14] R. Nutt, “Digital time intervalometer,” Rev. Sci. Instrum, vol. 39, no. 9, pp. 1342-1345, 1968.
[15] J. Kalisz, R. Szplet, J. Pasierbinski, A. Ponieck, “Field-programmable-gate-array- based time-to-digital converter with 200-ps resolution,” IEEE Trans. Instrum. Meas., vol. 46, pp. 71-75, 1997.
[16] M. S. Andaloussi, M. Boukadoum, and E.-M. Aboulhamid, “A novel time-to-digital converter with 150 ps time resolution and 2.5 ns pulse-pair resolution,” in Proc. 14th Int. Conf. Microelectron., 2002, pp. 123–126.
[17] R. B. Staszewski et al., “1.3V 20ps time-to-digital converters for frequency synthesis in 90-nm CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 3, pp. 220–224, Mar. 2006.
[18] J. Kalisz, R. Szplet, R. Pelka, A. Poniecki, “Single-Chip Interpolating Time Counter with 200-ps Resolution and 43-s Range,” IEEE Trans. Instrum. Meas., vol. 46, no. 4, pp. 851-856, Aug. 1997.
[19] J. Wu, Z. Shi, and I. Y. Wang, “Firmware-only Implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA),” in Proc. IEEE Conf. Rec. NSS., vol. 1, 2003, pp. 177–181.
[20] J. Song, Q. An, S. Liu, “A High-Resolution Time-to-Digital Converter Implemented in Field-Programmable-Gate-Arrays,” IEEE Trans. on Nuclear Science, vol. 53, no. 1, pp. 236-241, Feb. 2006.
[21] M. W. Fishburn, L. H. Menninga, C. Favi, and E. Charbon, “A 19.6 ps, FPGA-Based TDC With Multiple Channels for Open Source. Applications,” IEEE Trans. Nucl. Sci., vol. 60, no. 3, pp. 2203–2208, Jun. 2013.
[22] J. Wang, S. Liu, Q. Shen, H. Li, and Q. An, “A fully fledged TDC implemented in field-programmable gate arrays,” IEEE Trans. Nucl. Sci., vol. 57, no. 2, pp. 446–450, Apr. 2010.
[23] J. Wu, Z. Shi, “The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay,” IEEE Nucl. Sci. Symp. Conf. Rec., pp. 3440-3446, 2008.
[24] Yuan-Ho Chen, “A High Resolution FPGA-based Merged Delay Line TDC with Nonlinearity Calibration, ” IEEE International Symposium on Circuits and Systems, pp. 2432-2435, 2013.
[25] “Quartus II Handbook Version 13.1 ,” http://www.altera.com
[26] 蔡為翔,2014,以現場可程式化閘陣列實現延遲迴繞法搭配相位排序法之高精度時間至數位轉換器,碩士論文,國立台灣科技大學電子工程系研究所。
[27] 賴威諭,2011,以現場可程式化閘陣列實現延遲迴繞法為基礎之時間至數位轉換器,碩士論文,國立台灣科技大學電子工程系研究所。
[28] Poki Chen, Shen-Iuan Liu, and Jingshown Wu, “A CMOS Pulse-Shrinking Delay Element for Time Interval Measurement,” IEEE CAS-II, vol. 47, no. 9, pp. 954-8, Sep.2000.
[29] “StratixIV Device Handbook“ available from the Altera Corporation,” http://www.altera.com
[30] “Stratix10 Device Overview “ available from the Altera Corporation,” http://www.altera.com
[31] “Quartus II Handbook Version 14.0,” http://www.altera.com/literature/hb/qts/quartusii_handbook.pdf.
[32] “Quartus II Help v14.0,” http://quartushelp.altera.com/current/.
[33] P. Chen, C.-C. Chen, and Y.-S. Shen, “A Low Cost Low Power CMOS Time-to-Digital Converter Based on Pulse Stretching,” IEEE Trans. Nucl. Sci., vol. 53, no.4, pp.2215-2220, Aug. 2006.
[34] Poki Chen, Hsiu Che Cheng, Widodo, A., Wei Xiang Tsai, “A PVT insensitive field programmable gate array Time-to-Digital Converter,” IEEE Nordic Mediterranean Workshop on Time to Digital Converters, Oct. 2013.
[35] 林智民,2014,以現場可程式化閘陣列實現多重計數器為基礎之時間至數位轉換電路,碩士論文,國立台灣科技大學電子工程系研究所。
[36] R. Pelka, J. Kalisz, R. Szplet, “Nonlinearity correction of the integrated time-to-digital converter with direct coding, ” IEEE Trans. Instrum. Meas. vol. 46, pp. 449-453, 1997.
[37] R. Szplet, K. Klepacki, “An FPGA-integrated time-to-digital converter based on two-stage pulse shrinking,” IEEE Trans. Instrum. Meas., vol. 59, no. 6, pp. 1663-1670, Jun. 2010.
[38] S.S. Junnarkar, P. O'Connor, P. Vaska, R. Fontaine, “FPGA-based self-calibrating time-to-digital converter for time-of-flight experiments,” IEEE Trans. Nucl. Sci., vol. 56, no. 4, pp. 2374-2379, Aug. 2009.
[39] P. Chen, M.-C. Shie, Z.-Y. Zheng, Z.-F. Zheng and C.-Y. Chu, “A Fully Digital Time Domain Smart Temperature Sensor Realized with 140 FPGA Logic Elements,” IEEE Transactions on Circuits and Systems I, vol.54, no 12, pp. 2661-2668, Dec. 2007.
[40] Poki Chen, Po-Yu Chen, Juan-Shan Lai and Yi-Jin Chen, “FPGA Vernier Digital-to-Time Converter with 1.58ps Resolution and 59.3 Minutes Operation Range,” IEEE Transactions on Circuits and Systems I, vol. 57, no 6, pp.1134-1142, Jun. 2010.
[41] J. Christiansen, “An Integrated high resolution CMOS timing generator based on an array of delay locked loops,” IEEE Journal of Solid-State Circuits, Vol.31, pp. 952-957, July 1996.
[42] R. Ginosar, “Metastability and Synchronizers: A Tutorial,” Design & Test of Computers, IEEE vol. 28 , no. 5, pp. 23-35, Sept./Oct. 2011.
[43] Mohit Arora, ” The Art of Hardware Architecture: Design Methods and Techniques for Digital Circuits,” Springer, 2012.
[44] M. Morris Mano, “Digital Design, Third Edition, ” Prentice Hall, 2002.
[45] T.-H. Chao, Y.-C. Hsu, J.-M. Ho, D. K. Boese, B. A. Kahng, “Zero skew clock routing with minimum wirelength,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, pp. 799-814, 1992.
[46] F. D. Wann, A. M. Franklin, “Asynchronous and Clocked Control Structures for VSLI Based Interconnection Networks,” IEEE Transactions on Computers, vol. C-32, pp. 284-293, 1983.
[47] Ming-Bo Lin, Digital System Designs and Practices: Using Verilog HDL and FPGAs, John Wiley & Sons, 2008.
[48] “Agilent Technologies 81133A and 81134A 3.35 GHz Pulse Pattern Generators Data Sheet Version 1.2,” available from Agilent Corporation, http://www.home.agilent.com/.
[49] “Datasheet: Digital Phosphor Oscilloscopes and Digital Serial Analyzers,” available fromAgilentCorporation,www2.tek.com/cmswpt/madetails.lotr?ct=MA&cs=mur&ci=14588&lc=EN.
[50] Minjae. Lee and A. A. Abidi, “A 9b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 769–777, Apr. 2008.
[51] P. Lu, A. Liscidini, and P. Andreani, “A 3.6 mW, 90 nm CMOS gated-Vernier time-to-digital converter with an equivalent resolution of 3.2 ps,”IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1626–1635, Jul. 2012.
[52] S. J. Kim, W. Kim, M. Song, J. Kim, T. Kim and H. Park, “A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology,” Solid- State Circuits Conference - (ISSCC), 2015 IEEE International, San Francisco, CA, 2015, pp. 1-3.
[53] W. Pan, G. Gong, J. Li, “A 20-ps Time-to-Digital Converter (TDC) Implemented in Field-Programmable Gate Array (FPGA) with Automatic Temperature Correction,” IEEE Trans. Nucl. Sci., vol. 61, no. 3, pp. 1468–1473, Jun. 2014.
[54] L. Zhao, X. Hu, and S. Liu, J. Wang, Q. Shen, H. Fan, and Q. An, “The Design of a 16-Channel 15 ps TDC Implemented in a 65 nm FPGA,” IEEE Trans. Nucl. Sci., vol. 60, no. 5, pp. 3532–3536, Oct. 2013.
[55] S. J. Kim, W. Kim, M. Song, J. Kim, T. Kim, and H. Park,“15.5 A 0.6 V 1.17 ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14 nm FinFET technology,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), San Francisco, CA, USA, Feb. 2015,pp. 1–3.
[56] J. Wu, Z. Wang, C. Chen, C. Huang, and M. Zhang, “A 2.4-GHz all-digital PLL with a 1-ps resolution 0.9-mW edge-interchanging-based stochastic TDC,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 62,no. 10, pp. 917–921, Oct. 2015.
[57] A. Samarah and A. C. Carusone, “A digital phase-locked loop with calibrated coarse and stochastic fine TDC, ” IEEE J. Solid-State Circuits,vol. 48, no. 8, pp. 1829–1841, Aug. 2013.