本論文採用
TSMC 90 奈米 CMOS 技術 設計與 實現應用於 自旋 量子 位元 運算
之次取樣鎖相迴路 。作為量子電腦控制器的關鍵電路，此 電路 包含了次取樣相位
檢測器、次取樣電流泵、迴路濾波器及電壓控制振盪器。此電壓控制振盪器 可操
作頻率範圍為 18. 38 GHz 到 18. 5 7 GHz ，相位雜訊在 1 MHz 的偏移頻率下為
10 3.55 dBc/Hz ，功耗為 2.3 mW 。此次取樣鎖相迴路 可 提供 18.5 GHz 的信號，頻
帶內之相位雜訊為 114.34 dBc/Hz ，頻帶外之相位雜訊 在 10 MHz 的頻率偏移下
為 125.42 dBc/ H z 。此晶片功 率消耗 為 20.61 mW ，面積為 1.01 mm 2 。

A 18.5 GHz sub
sampling phase locked loop (SSPLL) is designed and
implemented using TSMC 90 nm CMOS technology for the application of
semiconductor spin qubit quantu m computers. As the key building block of the
controller of the quantum computer, this SSPLL contains the sub sampling phase
detector ( SSPD), sub sampling charge pump ( SSCP), loop filter and the voltage control
oscillator(VCO). The VCO covers the output tuni ng range from 18.38 18.57 GHz and
achieves the phase noise of 103.55 dBc/Hz at 1 MHz offset by consuming the power
of 2.3 mW.
The SSPLL is adopted to develop the 18.5 GHz signal with the in
band phase noise
of 114.34 dBc/Hz and the out band phase noise of 125.42 dBc/Hz at 10 MH z offset
at 300 K by consuming the power of 20.61 mW and the chip area of 1.01 mm 2 for spin
qubit quantum computing controller system.

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