本論文使用TSMC 90奈米CMOS技術實現應用於量子運算之單晶片低雜訊次取樣鎖相迴路，電壓控制振盪器的可操作頻率範圍為18.08 GHz到18.38GHz，相位雜訊在1 MHz的偏移頻率下為-104.7 dBc/Hz ~ -105.6 dBc/Hz， 此電路在頻帶內之相位雜訊在100 kHz的偏移頻率下為-93.5 dBc/Hz，頻帶外之相位雜訊在10 MHz的偏移頻率下約為 -123.5 dBc/Hz。在電路完成鎖定後，此時電路的功耗為68.4 mW；根據模擬結果，系統的鎖定時間約為3 μs，晶片面積為1.9mm2。

A 18.3 GHz sub-sampling PLL is implemented using TSMC 90-nm CMOS technology to generate microwave signal for quantum computers. The on-chip VCO achieves the tuning range from 18.08 GHz to 18.39 GHz, and exhibits the phase noise of -104.7 ~ -105.6 dBc/Hz at 1 MHz frequency offset, from the 18.08 GHz to 18.39 GHz carriers. Consuming the power of 64.8 mW and the chip area of 1.9 mm^2, the sub-sampling PLL delivers the 18.3 GHz signal with the in-band phase noise of -93.5 dBc/Hz and the out-band phase noise is -123.5 dBc/Hz at 10 MHz frequency offset. The locking time is 3 μs.

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