本論文研究適用於5G行動通訊技術頻段之雙頻帶頻率合成器，設計了包含混頻器之整數型頻率合成器，在各國已發表的5G預計頻帶如韓國三星之28GHz頻帶、日本docomo之11GHz頻帶以及美國Intel公司之38GHz頻帶。此雙頻帶整數型頻率合成器為參考韓國三星之28GHz頻帶和美國Intel公司之38GHz頻帶而設計，混頻器會將震盪器訊號以及振盪器除頻過後的訊號升頻產生1.5倍或1.125倍的振盪器訊號，輸出28 GHz 頻帶或是 38GHz頻帶的頻率。
本論文之雙頻帶整數型頻率合成器使用台積電TN90GUTM製程。其中震盪器的操作電壓在1.2V，功率消耗為29.64 mW，振盪器的頻率為23.96 GHz ~ 28.29 GHz，相位雜訊為-103.19 ~ -109.72 dBc/Hz@1 MHz;相位雜訊為 -120.78 ~ -134.20 dBc/Hz@10 MHz。量測鎖相迴路時，操作電壓會提高到1.8 V和1.6 V，功率消耗為281.55 mW，晶片面積為3.276 mm2，為281.55 mW，米勒除頻器可除範圍為23.9 GHz~27.2 GHz。鎖相迴路的輸出相位雜訊量測結果為 -67.59 ~ -87.39 dBc/Hz @1 MHz; -110.52~ -128.19 dBc/Hz @10 MHz。量測的鎖定時間約為2~8 us。

This thesis investigated frequency synthesizers for fifth-generation mobile communications technology. We designed a Dual band integer-N frequency synthesizer including mixers. The expecting frequency bands in 5G were 28 GHz from Samsung in Korea, 11 GHz from DOCOMO in Japan and 38GHz from Intel in USA. This Dual band integer-N frequency synthesizer referred to 28GHz from Samsung and 38 GHz from Intel. An up-conversion mixer is used to multiply the output signals from the VCO and the divider that follows the VCO to generate a signal at 1.5 times or 1.125 times the oscillating frequency of the VCO.
This dual band integer-N frequency synthesizer was designed in the TN90GUTM process. The supply voltage were 1.2 V when we only measured VCO, and the VCO power consumption was 29.64 mW. The tuning frequency of the VCO was from 23.96 GHz to 28.29 GHz. The measurement results of VCO phase noise is -103.19 ~ -109.72 dBc/Hz@1 MHz; -120.78 ~ -134.20 dBc/Hz@10 MHz. The supply voltage were 1.8 V and 1.6 V when we measured phase-locked loop, the total power consumption was 281.55 mW and the chip size is 3.276 mm2. The dividing range odf miller divider was from 23.96 GHz to 27.2 GHz. The measurement results of PLL phase noise is -67.59 ~ -87.39 dBc/Hz@1 MHz; -110.52 ~ -128.19 dBc/Hz@10 MHz. The measurement locking time was about 2~8 us.

[1] B. Sadhu, M. Ferriss, A. Natarajan, S. Yaldiz, J. O. Plouchart, A. Rylyakov, A. Valdes-Garcia, B. Parker, A. Babakhani, S. Reynolds, X. Li, L. Pileggi, R. Harjani, J. Tierno and D. Friedman, "A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing", IEEE J. Solid-State Circuits, vol. 48, no. 5, pp. 1138-1150, 2013
[2] Y. Wachi, P. Nagasku, H. Kondoh, "A 28 GHz low-phase-noise CMOS VCO using an amplitude-redistribution technique", Proc. IEEE Int. Solid-State Circuits Conf., pp. 482-483, 2008.
[3] C.-H. Chiu, K.-H. Liang, H.-Y. Chang et al., "A Low Phase Noise 26-GHz Push-Push VCO with A Wide Tuning Range in 0.18μm CMOS Technology," Asia-Pacific Microwave Conf., pp. 1131-1134, Dec. 2006.
[4] Tasic, W. Serdijn, "Concept of quasi-capacitive tapping of bipolar voltage-controlled oscillators", Proc. Int. Conf. Electron. Circuits Syst., vol. 1, pp. 93-96, 2002.
[5] T. D. Loveless; S. Jagannathan; E. X. Zhang; D. M. Fleetwood; J. S. Kauppila; T. D. Haeffner; L. W. Massengill, "Combined Effects of Total Ionizing Dose and Temperature on a K-Band Quadrature LC-Tank VCO in a 32 nm CMOS SOI Technology", IEEE Transactions on Nuclear Science, vol.64, pp.204-211,2017
[6] J.-O. Plouchart, "A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS", IEEE Trans. Circuits Syst. I, vol.60, pp. 2009-2017, 2013-Aug.
[7] J. Lee, M. Liu and H. Wang, "A 75-GHz phase-locked loop in 90-nm CMOS technology", IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1414-1426, 2008
[8] Jing Zhang, Navneet Sharma, Kenneth K. O, "21.5-to-33.4 GHz Voltage-Controlled Oscillator Using NMOS Switched Inductors in CMOS", Microwave and Wireless Components Letters IEEE, vol. 24, pp. 478-480, 2014, ISSN 1531-1309
[9] Pawan Agarwal, Partha Pratim Pande, Deukhyoun Heo, "25.3 GHz 4.1 mW VCO with 34.8% tuning range using a switched substrate-shield inductor", Microwave Symposium (IMS) 2015 IEEE MTT-S International, pp. 1-4, 2015.
[10] J. F. Osorio, C. S. Vaucher, B. Huff, E. v. d. Heijden and A. de Graauw, "A 21.7-to-27.8GHz 2.6-degrees-rms 40Mw frequency synthesizer in 45nm CMOS for mm-Wave communication applications," 2011 IEEE International Solid-State Circuits Conference, San Francisco, CA, 2011, pp. 278-280.
[11] J. Luo, L. Zhang, L. Zhang, Y. Wang and Z. Yu, "A 24GHz low power and low phase noise PLL frequency synthesizer with constant KVCO for 60GHz wireless applications," 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015, pp. 2840-2543.
[12] Yuanyuan Xu, Wei Wang, Wei Li, Dan Wu and Lai He, "A wideband LC VCO with small gain variation for 24GHz FMCW frequency synthesizer," 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Hangzhou, China, 2016, pp. 1437-1439.
[13] P. Y. Wang et al., "Design of 24GHz CMOS VCO using armstrong topology with asymmetric transformer," 2014 Asia-Pacific Microwave Conference, Sendai, Japan, 2014, pp. 956-958.
[14] W. El-Halwagy, A. Nag, P. Hisayasu, F. Aryanfar, P. Mousavi and M. Hossain, "A 28GHz quadrature fractional-N synthesizer for 5G mobile communication with less than 100fs jitter in 65nm CMOS," 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), San Francisco, CA, 2016, pp. 118-121.

[15] M. Ferriss, A. Rylyakov, J. A. Tierno, H. Ainspan and D. J. Friedman, "A 28 GHz Hybrid PLL in 32 nm SOI CMOS," in IEEE Journal of Solid-State Circuits, vol. 49, no. 4, pp. 1027-1035, April 2014.
[16] T. Siriburanon et al., "A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular," ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), Graz, 2015, pp. 76-79.
[17] T. Y. Lin, T. Y. Yu, L. W. Ke and G. K. Dehng, "A low-noise VCO with a constant KVCO for GSM/GPRS/EDGE applications," 2008 IEEE Radio Frequency Integrated Circuits Symposium, Atlanta, GA, 2008, pp. 387-390.
[18] N. Chen, L. Huang, C. Wang, Y. Yan and F. Lin, "Low phase noise and linear gain VCO using self-switched biasing," 2011 IEEE International Symposium on Radio-Frequency Integration Technology, Beijing, 2011, pp. 137-140
[19] P. Park, D. Park and S. Cho, "A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL," in IEEE Journal of Solid-State Circuits, vol. 47, no. 10, pp. 2433-2443, Oct. 2012.
[20] J. Lee, M. Liu and H. Wang, "A 75-GHz phase-locked loop in 90-nm CMOS technology", IEEE J. Solid-State Circuits, vol. 43, no. 6, pp. 1414-1426, 2008
[21] J. Lee and B. Razavi, "A 40-GHz frequency divider in 0.18-μm CMOS technology," in IEEE Journal of Solid-State Circuits, vol. 39, no. 4, pp. 594-601, April 2004.
[22] R. Nonis, E. Palumbo, P. Palestri and L. Selmi, "A Design Methodology for MOS Current-Mode Logic Frequency Dividers," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 2, pp. 245-254, Feb. 2007.

[23] T. H. Lin, C. L. Ti and Y. H. Liu, "Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-N PLLs," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 877-885, May 2009.
[24] Hung-Ming Chien et al., "A 4GHz Fractional-N synthesizer for IEEE 802.11a," 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525), 2004, pp. 46-49.
[25] S. Pellerano , R. Mukhopadhyay , A. Ravi , J. Laskar and Y. Palaskas, "A 39.1-to-41.6 GHz delta-sigma fractional-N frequency synthesizer in 90 nm CMOS", 2008 IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 484-630, 2008
[26] Q. Wu et al., "Frequency Tuning Range Extension in LC-VCOs Using Negative-Capacitance Circuits," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no. 4, pp. 182-186, April 2013.
[27] Tuan-Anh Phan, Chang-Wan Kim, Sang-Gug Lee, T. J. Park and E. J. Kim, "Gain mismatch-balanced I/Q down-conversion mixer for UWB," 2006 IEEE International Symposium on Circuits and Systems, Island of Kos, 2006, pp. 4 pp.-4990.
[28] Behzad Razavi, “Design of Analog CMOS Integrated Circuit”, McGraw-Hill, pp. 520-522, 2001.
[29] 楊育哲, “CMOS單晶片分數型鎖相迴路頻率合成器之設計與應用”, 國立臺灣大學電子所博士論文, June. 2007.