本研究中提出了基於超級源極隨耦器的低通濾波器(SSF-LPF)以及基於自耦源極隨耦器的低通濾波器(SCSF-LPF)。本研究亦有探討三次項諧波與迴路增益之間的關係。本篇論文也提出了同時適用於SSF-LPF和SCSF-LPF的操作頻率外零點控制方法。四階橢圓(4th order Ellptic)的SSF-LPF採用TSMC 90 nm製程製作，在1.2 V的供應電壓下消耗功率為22.8 mW。藉由調整兩位元的數位控制碼，截止頻率變化範圍為從0.7 GHz至1.2 GHz。在單端輸入100 MHz且峰對峰值為0.5V的信號時，總諧波失真為-41 dB。Noise Figure在10 MHz到1.2 GHz為20.8 – 38.5 dB。晶片面積包含PAD為2.184 mm2，只計SSF-LPF的話則為0.099mm2。四階的SCSF-LPF採用TSMC 40 nm LP製程製作。在1.1 V的供應電壓下消耗功率為13.64 mW。截止頻率為350 MHz。THD在差動輸入300 MHz且峰對峰值為1 V時達到-32 dB。SCSF-LPF的Noise Figure在10 MHz到350 MHz時為9.7 – 33.5 dB。晶片面積為0.518mm2。

In this thesis, a 4th-order elliptic super-source-follower based low-pass-filter (SSF-LPF) and a 4th-order self-coupled-source-follower based LPF (SCSF-LPF) are present. The relationship between third order harmonics and loop gain is investigated in this thesis. An out-of-band transmission zero control method for SSF-LPF and SCSF-LPF is proposed. The SSF-LPF is fabricated in TSMC 90 nm process. The power consumption of the SSF-LPF is 22.8 mW from a 1.2 V power supply. By controlling a 2 bit digital codes, the cut-off frequency can be varied from 0.7 GHz to 1.2 GHz. -41 dB of Total harmonic distortion (THD) is achieved for a 0.5 Vpeak-to-peak input signal at 100 MHz. The SSF-LPF achieves 20.8-38.5 dB noise figure. The chip area is 2.184 mm2. The SSF-LPF occupies 0.099 mm2 chip area without pads. The 4th-order SCSF-LPF is fabricated in TSMC 40 LP process. The power consumption of the SCSF-LPF is 13.64 mW from a 1.1 V power supply. The SCSF-LPF exhibits a cut-off frequency of 350 MHz. -32 dB of THD is achieved for a 1 Vpeak-to-peak differential input signal at 300 MHz. The SCSF-LPF achieves 9.7-33.5 dB noise figure. The chip area is 0.518 mm2.

[1] A. Osseiran, F. Boccardi, V. Braun, K. Kusume, P. Marsch, M. Maternia, O. Queseth, M. Schellmann, H. Schotten, H. Taoka et al., “Scenarios for 5g mobile and wireless communications: the vision of the metis project,” IEEE Communications Magazine, vol. 52, no. 5, pp. 26–35, 2014.
[2] P. Wan, Y. Chiu, and P. Lin, “A 5.8-mW, 20-MHz, 4th-order programmable elliptic filter achieving over- 80-dB IM3,” in Custom Integrated Circuits Conference (CICC), 2010 IEEE. IEEE, 2010, pp. 1–4.
[3] F. Houfaf, M. Egot, A. Kaiser, A. Cathelin, and B. Nauta, “A 65nm cmos 1-to-10ghz tunable continuous-time low-pass filter for high-datarate communications,” in 2012 IEEE International Solid-State Circuits Conference. IEEE, 2012, pp. 362–364.
[4] A. Tajalli and Y. Leblebici, “A widely-tunable and ultra-low-power mosfet-c filter operating in subthreshold,” in 2009 IEEE Custom Integrated Circuits Conference. IEEE, 2009, pp. 593–596.
[5] J. Botma, R. Wassenaar, and R. Wiegerink, “A low-voltage cmos op amp with a rail-to-rail constant-gm input stage and a class ab rail-torail output stage,” in Circuits and Systems, 1993., ISCAS’93, 1993 IEEE International Symposium on. IEEE, 1993, pp. 1314–1317.
[6] Xianping Fan and P. K. Chan, “Analysis and Design of Low-Distortion Source Follower”,IEEE Transactions on circuits and systems, Vol. 52, NO. 8, August 2005.
[7] Guangmao Xiing, Stephen H. Lewis, and T. R. Viswanathan, “Self Biased Unity-Gain Buffers with Low Gain Error”,IEEE Transactions on circuits and systems, Vol. 56, NO. 1, Jan 2009.
[8] I.Y. Lee, D. Im, J. Ko, and S. G. Lee,”A 50–450 MHz Tunable RF Biquad Filter Based on a Wideband Source Follower With > 26 dBm IIP ,+12 dBm P1dB , and 15 dB Noise Figure” in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 10, OCTOBER 2015
[9] De Matteis, M.; Pezzotta, A.; D'Amico, S.; Baschirotto, A., "A 33 MHz 70 dB-SNR Super-Source-Follower-Based Low-Pass Analog Filter,“ Solid-State Circuits, IEEE Journal of , vol.PP, no.99, pp.1,9
[10] S. D'Amico, et al. “A 255 MHz Programmable Gain Amplifier and Low-Pass Filter for Ultra Low Power Impulse-Radio UWB Receivers”, TCASI: Regular Paper: 59, no.2, Feb. 2012, pp. 337 – 345
[11] F. Houfaf, M. Egot, A. Kaiser, A. Cathelin, and B. Nauta, “A 65nm CMOS 1-to-10GHz tunable continuous-time low-pass filter for highdata-rate communications,” ISSCC Dig. Tech. Papers, pp. 362 –364, Feb 2012.
[12] J. Harrison and N. Weste, “A 500 MHz CMOS anti-alias filter using feed-forward op-amps with local common-mode feedback,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2003, pp. 132–483.
[13] L. Ye, H. Liao, C. Shi, J. Liu, and R. Huang, “A 2.3mA 240-to-500MHz 6th-order active-RC low-pass filter for ultra-wideband transceiver,” in Proc. IEEE Asian Solid State Circuits Conf. (A-SSCC), Beijing, China, Nov. 2010, pp. 1–4.
[14] M. S. S. Oskooei, N. Masoumi, M. Kamarei, and H. Sjoland, “A CMOS 4.35-mw +22-dBm IIP3 continuously tunable channel select filter for WLAN/WiMAX receivers,” IEEE J. Solid-State Circuits, vol. 46, no. 6, pp. 1382–1391, Jun. 2011.
[15] M. De Matteis, S. D’Amico, and A. Baschirotto, “A 0.55 V 60 dBDR fourth-order analog baseband filter,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2525–2534, Sep. 2009.
[16] S. D’Amico, et al. “A 6th-Order 100μA 280MHz Source-Follower-Based Single-loop Continuous-Time Filter” International Solid-State Circuits Conference 2008. Digest of Technical Papers. Page(s): 72-73.
[17] Yang Xu; Spencer Leuenberger; Praveen Kumar Venkatachala; Un-Ku Moon, “A 0.6mW 31MHz 4th-order low-pass filter with +29dBm IIP3 using self-coupled source follower based biquads in 0.18µm CMOS” IEEE Symposium on VLSI Circuits 2016.
[18]Behzad Razavi, “Design of Analog CMOS Integrated Circuit”, McGraw-Hill, pp. 520-522, 2001.