用於Ka頻段衛星通信的頻率合成器｜國立臺灣科技大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	邱立棟 Li-Tung Chiu
論文名稱：	用於Ka頻段衛星通信的頻率合成器 Frequency Synthesizer for Ka-band Satellite Communications
指導教授：	陳筱青 Hsiao-Chin Chen
口試委員:	楊成發 Chang-Fa Yang 陳文士 WUN-SHIH CHEN
學位類別：	碩士 Master
系所名稱：	電資學院 - 電機工程系 Department of Electrical Engineering
論文出版年：	2022
畢業學年度：	110
語文別：	中文
論文頁數：	51
中文關鍵詞：	Ka頻段、次取樣鎖相迴路、毫米波積體電路、衛星通訊
外文關鍵詞：	CMOS, Ka-band, satellite communication, sub-sampling PLL
相關次數：	點閱：361 下載：20
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

本論文使用TSMC 90奈米CMOS技術實現應用於Ka波段衛星通訊低雜訊次取樣鎖相迴路，原本預計做一個21.9 GHz到26.3 GHz的PLL，但因模擬有錯而使頻率不準，重新模擬後就能做出跟量測相似的的結果，量測結果為電壓控制振盪器的可操作頻率範圍為24.3 GHz到31 GHz，相位雜訊在1 MHz的偏移頻率下為-96.21 dBc/Hz ~ -81 dBc/Hz，此電路在25.3 GHz時頻帶內之相位雜訊在100 kHz的偏移頻率下為-78.27 dBc/Hz，頻帶外之相位雜訊在10 MHz的偏移頻率下約為 -110.01 dBc/Hz。在電路完成鎖定後，此時電路的功耗為168.516 mW；根據模擬結果，系統的鎖定時間約為90 μs，晶片面積為3.458 mm2。

A sub-sampling PLL is implemented using TSMC 90-nm CMOS technology to satellite communication systems in the Ka-band. The designing goal of the sub-sampling PLL was 21.9 ~26.3 GHz. But the frequency was inaccurate due to simulation error. After re-run the simulation, the simulation results are similar to measurement result. The on-chip VCO achieves the tuning range from 24.3 GHz to 31 GHz, and exhibits the phase noise of -96.21 ~ -81 dBc/Hz at 1 MHz frequency offset, from the 24.3 GHz to 31 GHz carriers. Consuming the power of 168.516 mW and the chip area of 3.458 mm^2, the sub-sampling PLL delivers the 25.3 GHz signal with the in-band phase noise of -78.27 dBc/Hz and the out-band phase noise is -110.01 dBc/Hz at 10 MHz frequency offset. The locking time is 90 μs.

摘要    II
Abstract    III
誌謝    IV
Contents    V
List of Figures    VI
List of Tables    VII
Chapter1 Introduction    1
1.1    Motivation    1
1.2    Organization    1
Chapter2 Circuit Structure and Design Flow of Low Phase Noise Sub-sampling PLL for Quantum Computing    3
2.1    The Basic structure of Sub-sampling PLL    3
2.2    Synthesizer Architecture    4
2.2.1    Phase Frequency Detector (PFD)+Dead Zone(DZ)    4
2.2.2    Sub-sampling Phase Detector (SSPD) and Sub-sampling Charge Pump (SSCP)    4
2.2.3    In-band Phase Noise Consideration    8
2.2.4    Pulser, Gm and AVCO    9
2.2.5    Loop Filter (LPF) and Charge Pump (CP)    11
2.2.6    Dead Zone Creator Design    15
2.2.7    Voltage Controlled Oscillator (VCO)    16
2.2.8    Miller Divider    20
2.3    Noise analysis of synthesizer architecture and system simulation result    25
2.3.1    Simulation result    25
Chapter3 Measurement results    26
3.1    Introduction    26
3.2    VCO measurement results    27
3.3    Sub-sampling PLL measurement results    30
3.4    Performance Summary    34
Chapter4 Conclusion    39
Reference    40
Appendix A    43

                                

[1] Brad Hall and Wyatt Taylor” Small Form Factor SATCOM Solutions”
[2] J. Lee and B. Razavi, "A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology," in IEEE Journal of Solid-State Circuits, vol. 39, no. 4, pp. 594-601, April 2004, doi: 10.1109/JSSC.2004.825119.
[3] X. Gao, E. A. M. Klumperink, M. Bohsali and B. Nauta, "A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N2" in IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3253-3263, Dec. 2009, doi: 10.1109/JSSC.2009.2032723.
[4] MSc. Thesis M.J.M. Wenting"Analysis Of Sub-Sampling Phase-Locked Loop Dynamic Behaviour"
[5] X. Gao, E. Klumperink and B. Nauta, "Sub-sampling PLL techniques," 2015 IEEE Custom Integrated Circuits Conference(CICC),2015,pp.1-8,doi: 10.1109/CICC.2015.7338420.
[6] G. Tiwari, M. U. Shaikh, S. Rudrapati and S. Gupta, "A Wide Locking Range Bleed-Current Injection-Enhanced Miller Divider in V-Band," 2020 IEEE Asia-Pacific Microwave Conference (APMC), 2020, pp. 908-910, doi: 10.1109/APMC47863.2020.9331702.
[7] Y. Lin and H. Wang, "A 35.7–64.2 GHz low power Miller Divider with Weak Inversion Mixer in 65 nm CMOS," in IEEE Microwave and Wireless Components Letters, vol. 26, no. 11, pp. 948-950, Nov. 2016, doi: 10.1109/LMWC.2016.2615013.
[8] G. Tiwari, S. Rudrapati and S. Gupta, "On optimization of miller divider with transformer injection enhancement," 2018 IEEE MTT-S International Wireless Symposium (IWS), 2018, pp. 1-4, doi: 10.1109/IEEE-IWS.2018.8400870
[9] M. K. Ali, V. Subramanian, T. Zhang and G. Boeck, "Design of Ka-band Miller divider in 130 nm CMOS," 2011 IEEE International Symposium on Radio-Frequency Integration Technology, 2011, pp. 205-208, doi: 10.1109/RFIT.2011.6141777.
[10] D. Shin, S. Raman and K. J. Koh, "2.8 A mixed-mode injection frequencylocked loop for self-calibration of injection locking range and phase noise in 0.13m CMOS," ISSCC 2016.
[11] V. Jain, S. K. Gupta, V. Khatri and G. Banerjee, "A 19.3-24.8 GHz Dual-Slope VCO in 65-nm CMOS for Automotive Radar Applications," 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), 2019, pp. 118-123, doi: 10.1109/VLSID.2019.00039.
[12] J. Rimmelspacher, R. Weigel, A. Hagelauer and V. Issakov, "36% Frequency-tuning-range dual-core 60 GHz push-push VCO in 45 nm RF-SOI CMOS technology," 2017 IEEE MTT-S International Microwave Symposium (IMS), 2017, pp. 1356-1358, doi: 10.1109/MWSYM.2017.8058865.
[13] Z. Yang, Y. Chen, S. Yang, P. Mak and R. P. Martins, "16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur," 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 270-272.
[14] T. Siriburanon et al., "A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad," in IEEE Journal of Solid-State Circuits, vol. 51, no. 5, pp. 1246-1260, May 2016
[15] Q. Shi, K. Bunsen, N. Markulic and J. Craninckx, "A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth," in IEEE Journal of Solid-State Circuits, vol. 54, no. 12, pp. 3503-3512, Dec. 2019.
[16] Y. -Y. Lin, F. -t. Chen and W. -Z. Chen, "A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect," 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2020
[17] J. Luo, L. Zhang, L. Zhang, Y. Wang and Z. Yu, "A 24GHz low power and low phase noise PLL frequency synthesizer with constant KVCO for 60GHz wireless applications," 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015, pp. 2840-2543
[18] X. Gao, E. A. M. Klumperink, M. Bohsali and B. Nauta, "A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N^2 ," in IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3253-3263, Dec. 2009.

簡易檢索 / 詳目顯示

相關論文