本論文提出6 GHz次取樣鎖相迴路(SSPLL)，可提供驅動Transmon量子電腦中Qubit的低雜訊微波信號。SSPLL使用TSMC90奈米CMOS技術實現。VCO涵蓋6.155 GHz到6.279 GHz，相位雜訊在1 MHz的偏移頻率下為-87.81 dBc/Hz，在10 MHz的偏移頻率下為-115.11 dBc/Hz。SSPLL的迴路頻寬為2 MHz，在頻帶內的相位雜訊在100 kHz的偏移頻率下為-112.44 dBc/Hz，在頻帶外的相位雜訊在10 MHz的偏移頻率下為-135 dBc/Hz。SSPLL的頻率雜訊是由2.5 kHz到 2.5 MHz的相位雜訊進行積分估算的結果，在室溫300 °K的情況下實現了3.6 kHzrms的頻率雜訊。SSPLL電路的整體功耗為20.1 mW，根據後模擬結果鎖定時間為1.5 μs，晶片面積為1.697 mm2。

A 6 GHz sub-sampling phase-locked loop (SSPLL) that delivers low-phase-noise microwave signals for qubit control in Transmon quantum computers is presented. The SSPLL is implemented using TSMC 90-nm CMOS technology. The VCO covers the frequency range from 6.155 GHz to 6.279 GHz and achieves the phase noises of -87.81 dBc/Hz at 1 MHz frequency offset and -115.11 dBc/Hz at 10 MHz frequency offset. Consuming the power of 20.1 mW and the chip area of 1.697 〖"mm" 〗^"2" , the SSPLL with the loop bandwidth of 2 MHz achieves the in-band phase noise of -122 dBc/Hz at 100 KHz frequency offset and the out-band phase noise is -135 dBc/Hz at 10 MHz frequency offset. The frequency noise of the SSPLL is estimated by integrating the phase noise from 2.5 kHz to 2.5 MHz for the quantum gate operation applied with the microwave pluse duration of 20 ns and Rabi frequency of 1 MHz. The SSPLL achieves the frequency noise of 3.6 kHzrms at 300 °K.

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