本論文研究適用於先進行動通訊技術頻段之頻率合成器，其一是符合現今LTE頻帶之串接式雙迴路三角積分調變分數型頻率合成器，台灣現今包含頻率範圍為0.7GHz到1.8GHz，而日本、韓國、歐洲、美國與中國所包含的頻率範圍從0.7GHz~0.9GHz及1.9 GHz~2.6GHz，此分數型頻率合成器可產生出以上述頻率範圍的兩至六倍頻(4.2 GHz~5.2 GHz)的頻率；同時為符合5G行動通訊技術頻帶我們設計了36-40GHz之分數型頻率合成器，在各國已發表的5G預計頻帶如韓國三星之28GHz及日本docomo之11GHz，此分數頻率合成器為參考美國Intel公司之38GHz頻帶而設計，可產生36GHz~40GHz的頻率。
本論文之串接式雙迴路三角積分調變分數型頻率合成器使用台積電0.18 μm CMOS製程實現，操作電壓在1.8 V與1.2 V，晶片面積為2.11 mm2，功率消耗74.04mW。第一級迴路使用可產生石英震盪器八倍頻率的注入鎖定式倍頻器當作第二級迴路的參考訊號，以此降低第二級迴路除數，進而使得迴路頻寬內的相位雜訊可以有效降低，並且將三角積分調變器的量化雜訊對系統的相位雜訊影響降到最小，量測結果在迴路頻寬內的輸出相位雜訊可以降低約-98.34 dBc/Hz@100 kHz，迴路頻寬外則為-127.5 dBc/Hz@7.5MHz。
本論文之36-40GHz分數型頻率合成器為設計電壓控制振盪器及除頻器之兩區塊電路，使用台積電TN90GUTM製程，操作電壓在1.2V，晶片面積為0.89 mm2，功率消耗27.23mW。振盪器振盪頻率為23.36 GHz~27.12 GHz，除頻器可除範圍為22.3GHz~27.4GHz，後模擬結果在預計相位頻寬內的輸出相位雜訊為123.7 ~127.8 dBc/Hz@10M。

This thesis investigated frequency synthesizers for advanced mobile communications technology. First, we designed a cascaded dual-loop delta-sigma modulation fractional-N frequency synthesizer for long term evolution applications. From the literature, we knew that the frequency range of long term evolution in Taiwan was from 0.7GHz to 1.8GHz. In addition, those of other countries, such as Japan, Korea, European countries, the United States and China, were from 0.7GHz to 0.9GHz and from 1.9 GHz to 2.6 GHz. Therefore, we designed the output frequency range of this fractional-N frequency synthesizer as two times to six times of the aforementioned frequencies (i.e., 4.2 GHz ~ 5.4 GHz); Meanwhile, we designed a 36-40GHz fractional-N frequency synthesizer for fifth-generation mobile communacations technology. The expecting frequency bands in 5G were 28 GHz from Samsung in Korea and 11 GHz from DOCOMO in Japan. This fractional-N frequency synthesizer referred to 38 GHz from Intel in USA, and covering 36GHz ~ 40GHz.
This cascaded dual-loop fractional-N frequency synthesizer was designed in the TSMC 0.18μm CMOS process. The supply voltages were 1.8 V and 1.2 V, the chip area was 2.11 mm2 and the total power consumption was 74.04mW. The first loop of the synthesizer was produced by the injection-locked frequency multiplier which can produce 8 times of frequency of crystal oscillator, by using the high output frequency of the first loop as the reference frequency of the second loop. The divided ratio of the second loop can be reduced, so that the outputin-band phase noise of this synthesizer can be reduced to -98.34 dBc/Hz@100 kHz. The out-of-band phase noise was -127.5 dBc/Hz@7.5MHz. Due to the high reference, quantization noise of delta-sigma modulation can be pushed to a much higher frequency, and thus the output phase noise will not be impacted by quantization noise more.
We designed two building blocks, which were a VCO and a divider in this 36 - 40 GHz fractional-N frequency synthesizer. These structures were designed in the TN90GUTM process. The supply voltage was 1.2 V, the chip area was 0.89 mm2 and the total power consumption was 27.23 mW. The tunning frequency of the VCO was from 23.36 GHz to 27.12 GHz, and the divided range of the divider was from 22.3 GHz to 27.4 GHz. The post-sim phase noise at 10 MHz which was the ecpected loop bandwidth resulted from 123.7 dBc/Hz to 127.8dBc/Hz.

[1] 楊育哲, “CMOS單晶片分數型鎖相迴路頻率合成器之設計與應用”, 國立臺灣大學電子所博士論文, June. 2007.
[2] P. Larsson,“A 2-1600MHz CMOS Clock recovery PLL with low-Vdd capability”,IEEE J. Solid-State Circuits, vol. 34,pp. 1951-1960, Dec.1999.
[3] W. Rhee,“Design of High Performance CMOS Charge Pumps in Phase-Locked Loops”,Proc. IEEE Int. Symp. Circuits and Systems, vol. 1, pp. 545-548, 1999.
[4] N. Nguyen and R. Meyer, “Start-up and frequency stability in high-frequency oscillators”,IEEE J. Solid-State Circuits, Vol. 27, No. 5, May. 1992.
[5] Toby K. K. Kan, Gerry C. T. Leung,and Howard C. Luong,“A 2-V 1.8-GHz Fully-Integrated CMOS Dual-Loop Frequency Synthesizer”,IEEE J. Solid-State Circuits, VOL. 37, NO. 8, AUGUST 2002.
[6] Z. Shu, K. L. Lee, and B. H. Leung, “A 2.4-GHz Ring-Oscillator-Based CMOS Frequency Synthesizer With a Fractional Divider Dual-PLL Architecture”,IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 452-462, March 2004.
[7] Ye, Z., Chen, W., Kennedy, M. P., “A novel dual-loop multi-phase frequency synthesizer”,Proc. European Conference on Circuit Theory and Design,Seville, Spain, pp. 567–570, 8/07
[8] T. Wu, P. Hanumolu, U. Moon, K. Mayaram, “An FMDLL based dual-loopfrequency synthesizer for 5 GHz WLAN applications”,Proceedings of ISCAS,pp. 3986-3989, Kobe, Japan, May 2005
[9] Hsiao-ChinChen, Wei-Kan Lee, “Battery-less ASK/O-QPSK Transmitter for Medical Implants”,IET Electronics Letters, Volume 48, Issue 17, pp.1036-1038, Aug. 2012.
[10] B. Mesgarzadeh and A. Alvandpour, “First-harmonic injection-locked ring oscillators”, Proc. IEEE Custom Integrated Circuit Conf. (CICC), pp.733 -736 2006
[11] B. Razavi, “A study of injection locking and pulling in oscillators”, IEEE J. Solid-State Circuits, vol. 39, no. 9, pp.1415 -1424 2004
[12] N. Fong, J.-O. Plouchart, N. Zamdmer, D. Liu, L. F. Wagner, C. Plett,and N. G. Tarr, “A 1-V 3.8–5.7-GHz wide-band VCO with differentiallytuned accumulation MOS varactors for common-mode noise rejection inCMOS SOI technology”,IEEE Trans. Microw. Theory Tech., vol. 51,no. 8, pp. 1952–1959, Aug. 2003.
[13] Ryan Lee Bunch and Sanjay Raman,“Large-signal analysis of MOS varactors in CMOS -Gm LC VCOs”,IEEE J. Solid-State Circuits, vol. 38, pp. 1325-1332, Aug. 2003.
[14] Emad Hegazi, Henrik Sjoland, Asad Abidi “A Filtering Technique to Lower Oscillator Phase Noise” ISSCC 2001 / SESSION 23 / ANALOG TECHNIQUES / 23.4, 2001
[15] M. H. Perrott, M. D. Trott, and C. G. Sodini, “A modeling approach for Delta-Sigmafractional-N frequency synthesizers allowing straightforward noise analysis”, IEEE J. Solid-State Circuits, vol. 37, pp.1028 -1038 2002
[16] 3GPP TS 36.101, http://www.3gpp.org/ftp/specs/html-info/36101.htm
[17] 3GPP,“Technical Specification Group Radio Access Network;User Equipment (UE) radio transmission and reception(Release 8)”,3GPP TS 36.101 V8.5.1.
[18] Yoohwan Kim, Byunghak Cho, Yoosam Na, “A Design of Fractional-N Frequency Synthesizer with Quad-Band (700 MHz/AWS/2100 MHz/2600 MHz) VCO for LTE Application in 65 nm CMOS Process”,Microwave Conference, 2009. APMC 2009. Asia Pacific.
[19] Nakyoon Kim, Yong Moon, “A Study on Wide-band Frequency Synthesizer for Advanced Wireless Communication”,SoC Design Conference (ISOCC), 2011 International.
[20] J. W. M. Rogers, F. F. Dai, M. S. Cavin, and D. G. Rahn, “A Multiband ΔΣfractional-N Frequency Synthesizer for a MIMO WLAN Transceiver RFIC”,IEEE J. Solid-State Circuits, vol. 40, no. 3, pp.678 -689 2005
[21] S. E. Meninger and M. H. Perrott, “A 1-MHz bandwidth 3.6 GHz 0.18-um CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise”, IEEE J. Solid-State Circuits, vol. 41, no. 4, pp.966 -980 2006
[22] C.C. Hung, D.S. Shen, S.I. Liu, “A 40GHz Fractional-N Frequency Synthesizer in 0. 13μm CMOS”,IEEE RFIC Symp. Dig., pp. 295-298, June 2008.
[23] C.-M. Hsu , M. Straayer and M. H. Perrott, “A low-noise wide-BW 3.6-GHz digital ΔΣfractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation”, IEEE J. Solid-State Circuits, vol. 43, no. 12, pp.2776 -2786 2008
[24] C.-Y. Yang , C.-H. Chang , J.-H. Weng and H.-M. Wu, “A 0.5/0.8-V 9-GHz frequency synthesizer with doubling generation in 0.13μm CMOS”,IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no. 2, pp.65 -69 2011
[25] Shekhar, S. et al., “A 2.4GHz Extended-Range Type-I ΔΣ Fractional-N Synthesizer with 1.8MHz Loop Bandwidth and -110dBc/Hz Phase Noise”, IEEE Trans. Circuits and Systems-II; Express Briefs, vol. 58, no. 8, pp. 472-476, August 2011
[26] Chih-Wei Yao, and Alan N. Willson, Jr., “A 2.8–3.2-GHz Fractional- Digital PLL with ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO”, IEEE J. Solid-State Circuits, VOL. 48, NO. 3, MARCH 2013
[27] Front cover – “IEEE Vehicular Technology Magazine Vehicular Technology Magazine”, IEEE Journals & Magazines Volume: 2, Issue: 3 10.1109/MVT.2007.4457885 ,Year: 2007
[28] Bodhisatwa Sadhu, Member, IEEE, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Member, IEEE, Jean-Olivier Plouchart, Senior Member, IEEE, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott Reynolds, Xin Li, Senior Member, IEEE, Larry Pileggi, Fellow, IEEE, Ramesh Harjani, Fellow, IEEE, Jose A. Tierno, and Daniel Friedman, Member, IEEE, “A Linearized, Low-Phase-Noise VCO-Based 25-GHz PLL With Autonomic Biasing,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 5, MAY 2013Z. Shu, K. L. Lee, and B. H. Leung, "A 2.4-GHz Ring-Oscillator-Based CMOS Frequency Synthesizer With a Fractional Divider Dual-PLL Architecture," IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 452-462, March 2004.
[29] Jri Lee, Member, IEEE, Mingchung Liu, and Huaide Wang ,” A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology. ” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 6, JUNE 2008
[30] J. Lee, B. Razavi, “A 40-GHz frequency divider in 0.18-μm CMOS technology,” IEEE Journal of Solid-State Circuits, Volume 39, Issue 4, Pages: 594 – 601, April 2004.
[31] S. Pellerano et al., “A 39.1-to-41.6 GHz fractional-N frequency synthesizer in 90 nm CMOS” in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2008, pp. 484–630.
[32] O. Richard et al., “A 17.5-to-20.94 GHz and 35-to-41.88 GHz PLL in 65 nm CMOS for Wireless HD Applications” in Proc. IEEE Int. SolidState Circuits Conf., 2010, pp. 252–253.
[33] W.-S. Chang, K.-W. Tan, and S.-H. Hsu, “A 56.5–72.2 Ghz transformer-injection Miller frequency divider in 0.13 m CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 7, pp. 393–395, Jul. 2010.
[34] M. K. Ali, V. Subramanian, T. Zhang, and G. Boeck, “Design of Ka-band Miller divider in 130 nm CMOS,” in IEEE Int. RF Integr. Technol. Symp., Nov. 2011, pp. 205–208.W.-S. Chang, K.-W. Tan, and S.
[35] T.-N. Luo and Y.-J. E. Chen, “A 0.8-mW 55-GHz dual-injection locked CMOS frequency divider,” IEEE Trans. Microw. Theory Techn., vol. 56, no. 3, pp. 620–625, Mar. 2008