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研究生: 丘濟昕
Ji-Shin Chiou
論文名稱: 氮化鎵之二/三倍頻輸出振盪器及注入鎖定除二/除六除頻器之研究
A Push/Triple Push GaN Oscillator and Divide-by 2 / by 6 Injection-Locked Frequency Divider
指導教授: 張勝良
Sheng-Lyang Jang
徐敬文
Ching-Wen Hsue
口試委員: 黃進芳
Jhin-Fang Huang
賴文政
Wen-Cheng Lai
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2017
畢業學年度: 105
語文別: 英文
論文頁數: 130
中文關鍵詞: 振盪器除頻器氮化鎵
外文關鍵詞: Oscillator, Divider, GaN
相關次數: 點閱:308下載:1
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  • 在RF射頻收發機中,頻率合成器的特性非常重要,內部包含了相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、壓控振盪器(VCO)、除頻器(FD),而這其中又以壓控振盪器和注入鎖定除頻器特性為主要電路。壓控振盪器需要低相位雜訊來避免相鄰雜訊訊號經由混波轉換的干擾,壓控振盪器的輸出在經由除頻器來達到降頻的工作,因此除頻器必須具有高的操作頻寬與頻率。本篇論文提出各兩種不同的除頻器與振盪器。
    首先,本論文提出一個台積電矽鍺0.18微米製程之寬除頻範圍除六注入鎖定除頻器,此除頻器使用p-core除二注入鎖定除頻器疊接n-core除三電容交叉耦合式注入鎖定除頻器所構成,除二與除三除頻器皆做為線性混波器之用。功率消耗為9.396mW,注入訊號強度為0dBm,可提供一個2.04GHz的鎖定頻寬,鎖定頻率從7.72GHz到9.76GHz,晶片面積為0.927x1.092 mm2.
    其次,本篇探討一個使用台積電0.18微米製程的四相位除二除頻器,注入功率從-21dBm~12dBm,並採用互感耦合訊號達到四相位輸出,此電路有兩個沒有重疊的鎖定範圍,若給較高注入功率或是高注入偏壓,晶片在低頻時會沒辦法正常運作。
    第三,本篇提出一個穩懋氮化鎵 0.25微米製程的振盪器並具有兩倍頻輸出,此電路採用兩個單端輸出的振盪器來產生差動輸出,並使用互感回授使其產生振盪,利用調整閘極與汲極的偏壓來改變振盪頻率與相位雜訊基頻為4.3GHz二次諧振為8.6GHz,期相位雜訊在1MHz時為-119.1dBc/Hz,功耗為98mW.晶片面積為2x1 mm2。
    最後,篇提出一個穩懋氮化鎵 0.25微米製程的振盪器並具有三倍頻輸出,此電路使用3個GaN HEMT放大器組成一個環型振盪器,三次諧振頻率為7.6GHz,相位雜訊再1MHz為-114.28dBc/Hz,功率消耗為386.456mW,晶片面積為2x1 mm2。


    In the RF transceiver, Frequency synthesizer is very important, its blocks include Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF),Voltage Controlled Oscillator (VCO), and Frequency Divider (FD), In order to pursue low-power, low phase noise, wide Locking range, the most important characteristics of performance are VCO and Divider,this thesis presents the design of voltage-controller oscillator (VCOs) and Injection-Locked Frequency Dividers (ILFDs).

    First, this thesis proposes a wide locking range ÷6 ILFD designed in the TSMC 0.18 μm BiCMOS process. The proposed current-reused ILFD is based on a low-frequency ÷2 p-core LC ILFD stacking on a high-frequency ÷3 n-core capacitive cross-coupled LC ILFD. Injection MOSFETS in ÷2 and ÷3 ILFDs are used as linear mixers. The injection signal is applied to the ÷3 ILFD first and the output is measured at ÷2 ILFD output. At power consumption Pdisp=9.396 mW, an external injected signal power of 0 dBm provides a locking range 2.04 GHz from 7.72 GHz to 9.76 GHz. The die area is 0.927 ×1.092 mm2.

    Secondly, we study a divide-by-2 transformer-coupled quadrature injection-locked frequency divider (QILFD) subject to injection power -21 dBm to 12 dBm. The ILFD consists of a transformer-coupled quadrature voltage controlled oscillator (QVCO) and two injection FETs, which are in parallel with the QVCO resonators for signal injection. The proposed CMOS ILFD has been implemented with the TSMC 0.18-μm CMOS technology. The QILFD has two non-overlapped locking ranges, the low-band locking range disappears at high injection power and high injection gate bias. The phase noise of the locked output spectrum is lower than that of free running QILFD in the 2 mode.

    Thirdly, this thesis designs a 0.25 μm GaN HEMT oscillator outputting a useful 2nd harmonic. The oscillator uses single-ended sub-oscillators configured in a balanced topology. The sub-oscillator uses transformer to provide output-to-input feedback to start the oscillation. The common nodes of the two sub-oscillators are virtual ground for the fundamental signals and provide outputs at the 2nd harmonic. The die area of the GaN HEMT oscillator is 2×1 mm2. The gate and drain biases are used to tune the oscillation frequency, they affect the low-frequency drain and gate current noises and phase noise of oscillator. The fundamental signal is at 4.3 GHz and the second harmonic signal is at 8.6 GHz. The phase noise is -119.1 dBc/Hz at the offset frequency of 1 MHz from the carrier at 8.62 GHz at the power consumption of 98 mW.

    Finally, we present a 0.25 μm GaN HEMT ring oscillator outputting a useful 3rd harmonic. The triple-push oscillator uses three HEMT amplifiers configured in a ring.The die area of the triple-push oscillator is 2×1 mm2. The gate and drain biases are used to tune the oscillation frequency. The third harmonic signal is at 7.6 GHz. The phase noise of -114.28 dBc/Hz at the offset frequency of 1 MHz from the carrier at 7.6 GHz at the power consumption of 386.456mW.

    摘要 Abstract 致謝 Table of Contents List of Figures List of Tables Chapter 1 Introduction 1.1 Background Chapter 2 Overview of Voltage Controlled Oscillators 2.1 Introduction 2.2 The Oscillator Theory 2.2.1 One Port (Negative Resistance) 2.2.2 Two-Port (Feedback) 2.3 Classification of Oscillators 2.3.1 Ring Oscillators 2.3.2 LC-tank Oscillators 2.3.3 Type of the LC Oscillator 2.3.4 Single Transistor Oscillator 2.3.5 Negative-Gm Oscillator 2.3.1 Cross-Coupled Oscillator 2.4 Passive Components Design 2.4.1 Inductors 2.4.2 Transformer 2.4.3 Capacitor 2.4.4 Varactors 2.5 Design Concepts of Voltage-Controlled Oscillator 2.5.1 Parameters of a Voltage-Controlled Oscillator 2.5.2 Phase Noise 2.52 Quality Factor Chapter 3 Design of Injection Locked Frequency Dividers 3.1 The dividers 3.2 Operation Principle 3.3 Injection Locking 3.4 Noise in ILOs 3.5 Locking Range 3.6 Example for a single injection of ILFD Chapter 4 Wide-Locking Range LC Divide-by-6 Injection-Locked Frequency Divider 4.1 Introduction 4.2 Circuit Design 4.3 Measurement Results Chapter 5 High-Injection-Level Property of Transformer-coupled Quadrature Injection-Locked Frequency Divider 5.1 Introduction 5.2 Circuit Design 5.3 Measurement Results Chapter 6 A Balanced 2nd Harmonic GaN HEMT Oscillator 6.1 Introduction 6.2 Circuit Design 6.3 Measurement Results Chapter 7 A GaN HEMT Triple-push Oscillator 7.1 Introduction 7.2 Circuit Design 7.3 Measurement Results Chapter 8 Conclusion References

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