時脈與資料回復電路(Clock and Data Recovery Circuit, CDR)廣泛的用於有線通訊系統。不論是從洲際間的光纖傳輸到通用序列匯流排(Universal Serial Bus, USB)，時脈與資料回復電路都是接收端中不可或缺的重要部分。近年來，個人行動裝置蓬勃發展，產品的輕薄短小成為最主要的重點。論文中，於時脈與資料回復電路中使用雙路徑(Dual-Path)的迴路濾波器，透過設計兩迴路的增益，可以有效的降低晶片中迴路濾波器的電容值，減少晶片面積。
與過去使用雙路徑的迴路濾波器相比，論文中設計避免使用運算放大器以及大電流的電流泵切換，而採用多重增益的壓控振盪器搭配雙路徑迴路濾波器。使用多重增益壓控振盪器的雙路徑迴路濾波器可以使時脈與資料回復電路系統的迴路頻寬設計不必受限於運算放大器的頻寬。此外迴路中避免較大電流的電流泵切換，亦可以降低迴路濾波器中的雜訊，使其具有較佳的抖動表現。設計兩個相差數倍的壓控振盪器增益，使兩迴路增益不同。迴路濾波器的極點以及零點，?b兩路徑迴路增益相差數倍的情況下，極點與零點的頻率亦會有該倍數的改變。經由妥善設計的兩個壓控振盪器增益相差倍數，可以有效的縮小迴路濾波器內的電容值。
與過去採用兩增益電流泵的雙路徑迴路濾波器時脈與資料回復電路相比，此論文使用多重增益壓控振盪器搭配雙路徑的迴路濾波器，由於在相位校正迴路內降低壓控振盪器的增益來達到電容放大效果，會使得相位校正迴路的頻率補償能力下降。因此，論文將頻率校正迴路獨立出來，並設計頻率校正迴路具有最大的壓控振盪器增益，用來克服製程變異。因此，論文中使用多重增益壓控振盪器搭配雙路徑的迴路濾波器不會因為頻率補償能力不足而造成無法達到目標頻率的問題。由於此設計將頻率校正迴路與相位校正迴路分離，因此得以對頻率鎖定迴路詳細分析並量測。論文內對無參考時脈的時脈資料回復電路內所廣泛使用的頻率偵測器(Frequency Detector, FD)操作行為進行了詳細的分析，以及鎖定時間的推導，最後亦經由量測結果驗證。
此電路使用標準0.18 m 1P6M CMOS製程實現。晶片內主動元件面積為0.4mm×0.38mm，被動元件為0.53mm×0.24mm，輸入樣本為PRBS 27-1的資料，量測其抖動(Jitter)峰對峰值為37.6ps；輸入樣本為PRBS 215-1的資料，量測其抖動峰對峰值為55.8ps；輸入樣本為PRBS 231-1的資料，量測其抖動峰對峰值為58.8ps。系統操作於2.5Gb/s，在供應電壓1.8V時，晶片消耗功率為67.5mW。

Clock and data recovery (CDR) circuit is used widely in data transmission system. From intercontinental communication to universal serial bus (USB), the CDR circuit always plays an important role in the receiver. In personal mobile products, the compact size is the priority. In this work, the dual-path loop filter is adopted to the CDR circuit. The proposed configuration of loop filter can reduce the on-chip capacitor size by a factor N in comparison with the traditional one.
Insead of operational amplifier (OPA) and high current gain charge pump in used dual-path loop filter, this design adopted the multi-gain voltage controlled oscillator (VCO). Without using OPA, the system loop bandwidth would not be limited by OPA’s loop bandwidth. Using low current gain charge pump can reduse the noise in loop filter, and it can bring the batter output jitter performance. By designing the multi-gain VCO properly, the different gain between the two paths in dual-path loop filter can be realized. The pole and zero frequency can be change by designing the different gain in dual-path loop filter. In other words, the capacitor value can be reduse by designing the multi-gain VCO appropriately.
Due to multi-gain VCO reduces the gain to achieve the capacitor multiplier, the ability of frequency compensation on phase tracking loop would be degrade. Therefore, this design adopted the independent frequency tracking loop. The frequency tracking loop has the maxmum VCO gain to overcome the process, voltage, temperature and load (PVTL) variations. The dual-path loop filter with multi-gain VCO can reach the target frequency by adding the frequency tracking loop. In this paper, the math model of frequency tracking loop was derived and proved because this system has the independent frequency tracking loop which can be measured.
This CDR circuit is implemented by standard 0.18-m 1P6M CMOS technology, and occupies active area of 0.4×0.38mm2 and a passive area of 0.53×0.24mm2. The retime clock peak-to-peak jitter measurement is 37.6ps when data pattern is PRBS 27-1. When data pattern is PRBS 215-1 and 231-1, the retime clock peak-to-peak jitter measurement is 55.8ps and 58.8ps. The power dissipation at 2.5 Gb/s is 67.5mW from a 1.8-V power supply.

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