電壓控制振盪器與除頻器為頻率合成器中之主要電路區塊，此兩者的操作頻率範圍決定頻率合成器之頻寬，因此在寬頻應用中需要寬頻電壓控制振盪器與除頻器。一個好的振盪器必須具有低相位雜訊之特性，以避免相鄰頻帶雜訊的混波轉換。注入鎖定除頻器經常被用作高頻除頻器，必須具有寬鎖定範圍之特性。
　　本論文提出一個電壓控制振盪器與一個注入鎖定除頻器，前者為使用聯電 90 奈米製程、具有33 %可調範圍之電壓控制振盪器，後者為使用台積電0.13微米製程、具有16.5 %鎖定範圍與35 %操作範圍之除三注入鎖定除頻器。以上兩者皆具有低消耗功率特性，所消耗之直流功率分別為1.32 mW與2.05 mW。
　　首先，我們提出一個寬可調範圍電壓控制振盪器，其使用堆疊式電感來解決標準數位製程中缺少厚金屬層之問題，降低振盪器的相位雜訊。同時，採用低臨界電壓電晶體與最佳化可調比的可變電容，獲得寬可調範圍與低製程變異。此電路之供應電壓為0.4 V，頻率為9.15 GHz至12.77 GHz，範圍為3.62 GHz。而在輸出頻率為10.13 GHz時，1 MHz偏移頻率下相位雜訊為 -108.78 dBc/Hz，figure of merit(FOM)為 -187.68 dBc/Hz，figure of merit with tuning range(FOMT)則為 -198.06 dBc/Hz。
　　其次提出的是一個寬鎖定範圍除三注入鎖定除頻器，其輸入電晶體作為線性混波電晶體，並且由電路本身獲得兩倍振盪頻率訊號來與輸入混波，改善傳統架構中有效次諧波訊號較小之問題，得到較寬的注入鎖定範圍。此電路供應電壓為1.3 V，消耗功率為2.05 mW。注入鎖定範圍在Vtune為1.3 V時由14.5 GHz至17.1 GHz，而調整Vtune由0 V至1.3 V可得到由12.0 GHz至17.1 GHz之工作範圍，鎖定範圍與工作範圍之百分比分別為16.5 %與35.1 %。

The voltage-controlled oscillator (VCO) and the frequency divider are main blocks of a frequency synthesizer’s. Bandwidth of a frequency synthesizer is dominated by operating frequency ranges of these two blocks, so we require wideband VCOs and frequency dividers for wideband applications. A good VCO must exhibit low-phase-noise characteristic to prevent noise in adjacent frequencies from being down-converted or up-converted. We generally apply an injection-locked frequency divider (ILFD) to perform frequency division at high frequency. The wider the locking range is, the better ILFD.
We present a voltage-controlled oscillator and an injection-locked frequency divider in this thesis. The former is a VCO with 33 % frequency tuning range and is fabricated in UMC 90 nm process. The latter is a divide-by-three ILFD with 16.5 % locking range and 35 % operation range. This ILFD is implemented in TSMC 0.13 process. Both of the proposed circuits are low-power as the power consumption of the VCO and the ILFD are 1.32 mW and 2.05 mW respectively.
At first, we present a wide-tuning-range VCO, which adopts stacked inductors to straighten out the absence of ultra-thick top metal in the standard digital process. Thus, the phase noise is lowered. Meanwhile, transistors with low threshold voltage and varactors with optimized tuning ratio are used to acquire a wide tuning range and low process variation. At the supply voltage 0.4 V, the tuning range is 3.62 GHz, ranging from 9.15 GHz to 12.77 GHz. Phase noise at 1 MHz offset frequency from the carrier frequency 10.13 GHz is -108.78 dBc/Hz. Figure of merit (FOM) and the figure of merit with tuning range (FOMT) are -187.68 dBc/Hz and -198.06 dBc/Hz respectively.
Then, a wide-locking-range divide-by-three ILFD is presented. Its input transistors act as linearly mixing transistors. A signal, of which the frequency is twice that of the free-running signal, is extracted by the circuit itself. This signal is mixed into the input of the ILFD to solve the problem that the subharmonic is too weak in conventional structure. This results in a wider locking range. At the supply voltage of 1.3 V, the power consumption is 2.05 mW. At Vtune of 1.3 V, the locking range is from 14.5 GHz to 17.1 GHz. The operation range is from 12.0 GHz to 17.1 GHz, while Vtune varies from 0 V to 1.3 V. Percentage of the locking range and the operation range are 16.5 % and 35.1 % respectively.

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