在無線通訊系統中，頻率合成器是用來做訊號頻率的升降之用。在頻率合成器電路裡，壓控振盪器是重要的核心電路之ㄧ。對壓控振盪器而言，必須提供低相位雜訊的輸出，以避免相鄰雜訊訊號經由混波轉換產生干擾。
本論文提出一個雙頻帶電壓控制振盪器、一個三相位壓控振盪器和一個四相位壓控振盪器。在第一個電路裡，它是個用電晶體當開關的雙頻帶電壓控制振盪器。第二個電路是個使用一種新型電感加上三推式耦合的三相位互補式考畢茲壓控振盪器。第三個電路中，我們提出一個使用N型電晶體共閘極耦合技術產生四相位輸出的壓控振盪器。
首先，一個雙頻帶的壓控振盪器使用台積電0.18微米製程實現雙頻輸出。壓控振盪器的低頻操作頻率從3.92 GHz到4.3 GHz而高頻操作頻率從6.34 GHz 到6.86 GHz且功率消耗為4.425 mW。而在輸出低頻頻率為4.26 GHz時，1 MHz偏移頻率下相位雜訊為 -124.46 dBc/Hz，在輸出高頻頻率為6.49 GHz時，1 MHz偏移頻率下相位雜訊為 -118.31 dBc/Hz，低頻的figure of merit為 -190.58 dBc/Hz且高頻的figure of merit為 -188.09 dBc/Hz，晶片面積1.16 × 1.12 mm2。
其次，一個 4.6 GHz的壓控振盪器使用台積電0.18微米製程實現三相位且在平衡的電路架構中使用三個相同的單端互補式考畢茲壓控振盪器和透過打線的電感效應耦合成三相位輸出。三相位壓控振盪器操作頻率從 4.59 GHz到 5.094 GHz且功率消耗為 10.764 mW。而在輸出頻率為 4.6 GHz時，1 MHz偏移頻率下相位雜訊為 -118.39 dBc/Hz，晶片面積 1.096 × 1.088 mm2且figure of merit為 -181.36 dBc/Hz。
最後，我們提出四相位壓控振盪器，使用common-gate電晶體取代common-source電晶體作為耦合元件，一個 3.8 GHz的壓控振盪器使用台積電0.18微米製程實現四相位使用兩組P型交錯耦合電晶體為和透過N型電晶體當作耦合元件。此電路的可調頻率為 3.65 GHz至 3.94 GHz。而在輸出頻率為3.8 GHz時， 1 MHz偏移頻率下相位雜訊為 -126.64 dBc/Hz且消耗功率為 7.24 mW。此電路的figure of merit為 -189.64 dBc/Hz，晶片面積 1.08 × 0.924 mm2。

In wireless communication system, frequency synthesizers are used to implement the frequency up/down converting of signal. In a frequency synthesizer, voltage-controlled oscillator (VCO) is the key block. For VCOs, low phase-noise output is required to avoid corrupting the mixer-converted signal by close interfering tones.
We present a dual-band VCO, a three-phase VCO and a Quadrature VCO in this thesis. In the first circuit, it’s a dual-band VCO using the transistor as the switch. The second circuit is a three-phase complementary colpitts VCO using the triple-push coupling and a novel inductor. In the third circuit, we proposed a VCO which provides quadrature outputs by NMOSFET common-gate -coupling technique.
Firstly, a dual-band VCO in 0.18 μm CMOS process is proposed to generate 2 output phases. The low-band of the VCO oscillates from 3.92 GHz to 4.3 GHz and the high-band of the VCO oscillates from 6.34 GHz to 6.86 GHz. The power consumption is 4.425 mW. The phase noise is -124.46 dBc/Hz at 1 MHz offset frequency from 4.26 GHz and the phase noise is -118.31 dBc/Hz at 1 MHz offset frequency from 6.49 GHz. A figure of merit of low-band is -190.58 dBc/Hz and a figure of merit of high-band is -188.09 dBc/Hz. The dual-band VCO occupies a chip area of 1.16 × 1.12 mm2.
Secondly, a prototype 4.6 GHz VCO in 0.18 μm CMOS process is proposed to generate 3 output phases and it uses three identical single-ended complementary Colpitts VCOs in a balanced configuration and coupled via the bonding inductors to provide 3-phase outputs. The 3-phase VCO oscillates from 4.59 GHz to 5.094 GHz and the power consumption is 10.764 mW. The phase noise is -118.39 dBc/Hz at 1 MHz offset frequency from 4.6 GHz. The VCO occupies a chip area of 1.096 × 1.088 mm2 and provides a figure of merit of -181.36 dBc/Hz.
Finally, we propose a fully-integrated quadrature cross-coupled voltage controlled oscillator (VCO) using common-gate transistor instead of common-source transistor as a coupling device. The prototype 3.8 GHz QVCO in 0.18 μm CMOS process is proposed to generate 4 output phases and it uses two p-core cross-coupled VCOs and nMOS coupling devices. The free-running frequency of the QVCO is tunable from 3.65 GHz to 3.94 GHz. The measured phase noise at 1 MHz frequency offset is -126.65 dBc/Hz at the oscillation frequency of 3.8 GHz and the total power consumption is 7.24 mW, the figure of merit (FOM) of the proposed QVCO is -189.64 dBc/Hz. The VCO occupies a chip area of 1.08 × 0.924 mm2.

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