本論文設計實現一顆14位元的數位至類比轉換器，採用電流導向式架構與一種構建多元件高精度匹配佈局的方法，來達到高速與高精度的性能。
這顆14位元電流導向式數位至類比轉換器使用分段式混合架構，高位元部分的8位元採用溫度計碼編碼方式，透過解碼器將輸入訊號的二進位元權重碼解碼成溫度計碼來控制電流源陣列，該電流源陣列使用修正式Q2隨機佈局樣式（Modified Quad Quadrant Random Pattern）之高精度匹配佈局來消除系統性不匹配的影響，並透過佈局自動化實現電流源陣列的佈局。低位元部分的6位元使用二進位元權重式編碼方式，透過本論文所提出電流分流器的高匹配性電流源架構，在增加解析度的同時，依舊保有較快之操作速度。
此數位至類比轉換器是由UMC 0.18um Mixed-Signal 1P6M製程來實現，操作於1.8V與3.3V的供應電壓下，積分非線性誤差為 ，轉換速率為100MHz，核心晶片面積為1.153mm2。

關鍵字：電流導向式數位至類比轉換器、系統性不匹配、修正式Q2隨機佈局樣式、佈局自動化

A 14-bit digital-to-analog converter （DAC）is prosed and implemented in this thesis. It adopts current-steering architecture and multi-element precision matching layout for high-speed and high-accuracy applications.
The proposed 14-bit high accuracy current-steering DAC utilizing segmented architecture. The eight-bit most significant bits are decoded from binary code to thermometer code by a thermometer decoder which steers the unary weighted current source array. The systematic mismatch of this current source array is canceled by highly matching layout called Modified Q2 Random Pattern created by our research team. The six-bit least significant bits are constructed as a binary weighted current source array implemented by current splitters also proposed by our team to enhance its accuracy.
The DAC is implemented in a UMC 0.18um Mixed-Signal 1P6M process powered with 1.8V/3.3V dual supplies. The integral nonlinearity and sampling frequency of the post-simulation are and 100 MHz respectively. The chip core area is merely 1.153mm2.
Keyword: Current-steering digital-to-analog converter，Systematic mismatch，Modified Q2 Random Pattern，Layout automation.

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