本論文設計實現一個具自我校正技術之十四位元電流導向式數位至類比轉換器，為了兼顧高速和高解析度之需求，本論文採用分段電流導向式架構(Segmented Current Steering)實現，高位元的部分使用單位電流源矩陣(Unary Current Source Matrix)進行實現，並搭配創新的循序漸進式(Successive Approximation Register)校正方式針對單位電流源進行前景式校正(Foreground Calibration)；而低位元的部分則採用分流器(Splitter)架構來實現二進制權重式電流源陣列(Binary Weighted Current Source Array)，其中分流器以搭配高精度佈局之複製-分割的高匹配電流鏡架構所組成。透過上述兩種架構與設計，以改善系統不匹配(Systematic Mismatch)與隨機性不匹配(Random Mismatch)所造成的電流誤差，進而取得高精度表現。
本論文設計之數位至類比轉換器使用TSMC 90nm 1P9M製程來實現，而供應電壓則以1.2 V進行操作，積分非線性誤差(INL)介於+0.37 LSB ~ -0.41 LSB，微分非線性誤差(DNL)介於+0.30 LSB ~ -0.01 LSB。在取樣頻率為250 MHz下，輸入頻率為124.5 MHz時，無雜散動態範圍(SFDR)為75.55 dB；當輸入頻率為1.04 MHz時，無雜散動態範圍則為94.74 dB，功率消耗約為39 mW，核心晶片面積約為1.19 mm2。

A 14-bit current-steering digital-to-analog converter with self-calibration is proposed and implemented in this thesis. In order to achieve high-speed and high-resolution, the segmented current-steering architecture is adopted. The most significant bits (MSB) adopt unary current source matrix with successive approximation register (SAR) mechanism for unit current source foreground calibration. The least significant bits (LSB) adopt current splitter architecture to achieve high accuracy binary weighted current source array. Moreover, the current-splitter is composed of high-precision current mirror realized with the second-order gradient cancellation layout. Through the help of those two techniques, the current error caused by systematic mismatch and random mismatch can be alleviated to accomplish high enough precision for the proposed 14-bit DAC.
The DAC is implemented in a TSMC 90 nm 1P9M CMOS technology and the operation voltage is 1.2 V. The integral nonlinearity (INL) and differential nonlinearity (DNL) are simulated to be +0.37 ~ -0.41 LSB and +0.30~ -0.01 LSB respectively. The DAC achieves a spurious free dynamic range (SFDR) of 75.55 dB for 124.5 MHz input frequency at 250 MHz sampling rate. For 1.04 MHz input frequency, the SFDR is 94.74 dB. The power consumption is 39 mW and the active area is merely 1.19 mm2.

[1] D. Marche, Y. Savaria, and Y. Gagnon, "Laser Fine-Tuneable Deep-Submicrometer CMOS 14-bit DAC," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 8, pp. 2157-2165, Sep. 2008.
[2] A. v. d. Bosch, M. A. F. Borremans, M. S. J. Steyaert, and W. Sansen, "A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter," IEEE Journal of Solid-State Circuits, vol. 36, no. 3, pp. 315-324, Mar. 2001.
[3] B. Schafferer and R. Adams, "A 3V CMOS 400mW 14b 1.4GS/s DAC for multi-carrier applications," in 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 15-19 Feb. 2004 2004, pp. 360-532 Vol.1.
[4] B. Jewett, J. Liu, and K. Poulton, "A 1.2GS/s 15b DAC for precision signal generation," in ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005., 10-10 Feb. 2005 2005, pp. 110-587 Vol. 1.
[5] A. v. Roermund et al., "A 12b 500MS/s DAC with >70dB SFDR up to 120MHz in 0.18μm CMOS," in ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005., 10-10 Feb. 2005 2005, pp. 116-588 Vol. 1.
[6] F. Chou, Z. Chen, and C. Hung, "A 10-bit 250MS/s low-glitch binary-weighted digital-to-analog converter," in 2014 27th IEEE International System-on-Chip Conference (SOCC), 2-5 Sept. 2014 2014, pp. 231-235.
[7] A. Hastings, The art of analog layout. Upper Saddle River, N.J: Pearson Education (in Dutch), 2006.
[8] H. Samueli, "Broadband communications ICs: enabling high-bandwidth connectivity in the home and office," in 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278), 17-17 Feb. 1999 1999, pp. 26-30.
[9] 劉沛潔, "通訊系統中數位類比轉換器之電路設計," 系統晶片, pp. 58-76, 2005.
[10] T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, "An 80-MHz 8-bit CMOS D/A converter," IEEE Journal of Solid-State Circuits, vol. 21, no. 6, pp. 983-988, Dec. 1986.
[11] Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, "A 10-b 70-MS/s CMOS D/A converter," IEEE Journal of Solid-State Circuits, vol. 26, no. 4, pp. 637-642, Apr. 1991.
[12] J. Bastos, M. Steyaert, and W. Sansen, "A high yield 12-bit 250-MS/s CMOS D/A converter," in Proceedings of Custom Integrated Circuits Conference, 5-8 May 1996 1996, pp. 431-434.
[13] J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, "A 12-bit intrinsic accuracy high-speed CMOS DAC," IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1998.
[14] L. Chi-Hung and K. Bult, "A 10-b, 500-MSample/s CMOS DAC in 0.6 mm/sup 2," IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 1948-1958, Dec. 1998.
[15] A. R. Bugeja, B. Song, P. L. Rakers, and S. F. Gillig, "A 14-b, 100-MS/s CMOS DAC designed for spectral performance," IEEE Journal of Solid-State Circuits, vol. 34, no. 12, pp. 1719-1732, Dec. 1999.
[16] G. A. M. V. D. Plas, J. Vandenbussche, W. Sansen, M. S. J. Steyaert, and G. G. E. Gielen, "A 14-bit intrinsic accuracy Q/sup 2/ random walk CMOS DAC," IEEE Journal of Solid-State Circuits, vol. 34, no. 12, pp. 1708-1718, Dec. 1999.
[17] C. Yonghua and R. L. Geiger, "A 1.5-V 14-bit 100-MS/s self-calibrated DAC," IEEE Journal of Solid-State Circuits, vol. 38, no. 12, pp. 2051-2060, Dec. 2003.
[18] T. Chen and G. G. E. Gielen, "A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration," IEEE Journal of Solid-State Circuits, vol. 42, no. 11, pp. 2386-2394, Nov. 2007.
[19] R. Liu and L. Pileggi, "Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 7, pp. 651-655, Jul. 2015.
[20] B. Razavi, Principles of data conversion system design. New York, N.Y.: IEEE (in English), 1995.
[21] K. Doris, v. A. H. M. Roermund, and D. M. W. Leenaerts, Wide-bandwidth high-dynamic range D/A converters. Springer (in English), 2006.
[22] L. Fang-Jie, Y. Yong-Sheng, L. Shang-Quan, and G. Ming-Lun, "Current switch driver and current source designs for high-speed current-steering DAC," in 2008 2nd International Conference on Anti-counterfeiting, Security and Identification, 20-23 Aug. 2008 2008, pp. 364-367.
[23] T. C. Carusone, D. Johns, and K. W. Martin, Analog integrated circuit design. (in English), 2013.
[24] A. S. Sedra, K. C. Smith, T. C. Carusone, and V. Gaudet, Microelectronic circuits. (in English), 2020.
[25] S. H. Yang, K.-S. Lee, S. Kim, and Y. M. Lee, "Charge-redistribution DAC with double bit processing in single capacitor," Electronics Letters, vol. 47, pp. 312-313, 04/03 2011.
[26] M. Un-Ku, J. Silva, J. Steensgaard, and G. C. Temes, "A switched-capacitor DAC with analog mismatch correction," in 2000 IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2000 2000, vol. 4, pp. 421-424 vol.4.
[27] A. V. d. Bosch, M. Steyaert, and W. Sansen, "An accurate statistical yield model for CMOS current-steering D/A converters," in 2000 IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2000 2000, vol. 4, pp. 105-108 vol.4.
[28] K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, "Characterisation and modeling of mismatch in MOS transistors for precision analog design," IEEE Journal of Solid-State Circuits, vol. 21, no. 6, pp. 1057-1066, Dec. 1986.
[29] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989.
[30] J. Bastos, M. S. J. Steyaert, A. Pergoot, and W. M. Sansen, "Influence of die attachment on MOS transistor matching," IEEE Transactions on Semiconductor Manufacturing, vol. 10, no. 2, pp. 209-218, May 1997.
[31] D. Xin, H. Chengming, X. Hanqing, C. Degang, and R. Geiger, "An N/sup th/ order central symmetrical layout pattern for nonlinear gradients cancellation," in 2005 IEEE International Symposium on Circuits and Systems, 23-26 May 2005 2005, pp. 4835-4838 Vol. 5.
[32] A. v. d. Bosch, M. Steyaert, and W. Sansen, "SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters," in ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), 5-8 Sept. 1999 1999, vol. 3, pp. 1193-1196 vol.3.
[33] K. O. Sullivan, C. Gorman, M. Hennessy, and V. Callaghan, "A 12-bit 320-MSample/s current-steering CMOS D/A converter in 0.44 mm/sup 2," IEEE Journal of Solid-State Circuits, vol. 39, no. 7, pp. 1064-1072, Jun. 2004.
[34] H. J. Schouwenaars, D. W. J. Groeneveld, and H. A. H. Termeer, "A low-power stereo 16-bit CMOS D/A converter for digital audio," IEEE Journal of Solid-State Circuits, vol. 23, no. 6, pp. 1290-1297, Dec. 1988.
[35] M. P. Tiilikainen, "A 14-bit 1.8-V 20-mW 1-mm/sup 2/ CMOS DAC," IEEE Journal of Solid-State Circuits, vol. 36, no. 7, pp. 1144-1147, Jul. 2001.
[36] I. Yusuke, M. Frey, and M. Akira, "A 14-bit 100-MS/s digitally calibrated binary-weighted current-steering CMOS DAC without calibration ADC," in 2007 IEEE Asian Solid-State Circuits Conference, 12-14 Nov. 2007 2007, pp. 356-359.
[37] C. Yu, H. Ching-Hsuan, S. Tim-Kuei, and C. Wen-Tzao, "A 90nm 10-bit 1GS/s current-steering DAC with 1-V supply voltage," in 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 23-25 April 2008 2008, pp. 255-258.
[38] H. Traff, "Novel approach to high speed CMOS current comparators," Electronics Letters, vol. 28, no. 3, pp. 310-312, 1992.
[39] L. Hongchin, H. Jie-Hau, and W. Shyh-Chyi, "A simple high-speed low current comparator," in 2000 IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2000 2000, vol. 2, pp. 713-716 vol.2.
[40] M. T. I. Badal, M. B. Mashuri, M. B. I. Reaz, N. Kamal, and F. H. Hashim, "Low power high-speed current comparator using 130nm CMOS technology," in 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering (ICAEES), 14-16 Nov. 2016 2016, pp. 72-76.
[41] J. E. M. Solis et al., "Low Input Resistance CMOS Current Comparator Based on the FVF for Low-Power Applications," Canadian Journal of Electrical and Computer Engineering, vol. 39, no. 2, pp. 127-131, May 2016.
[42] S. Hanfoug, N.-E. Bouguechal, and B. Samir, "Behavioral non-ideal Model of 8-bit Current-Mode Successive Approximation Registers ADC by using Simulink," International Journal of u- and e- Service, Science and Technology, vol. 7, pp. 85-102, 04/01 2014.
[43] F. H. Gebara, S. M. Martin, K. Nowka, and R. B. Brown, "Accurate current mirroring in the presence of gate leakage current," in 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573), 4-7 Oct. 2004 2004, pp. 117-118.
[44] B. Razavi, Design of analog CMOS integrated circuits. New York, NY: McGraw-Hill Education (in English), 2017.
[45] 游爵豪, "實現在90 奈米製程之低電壓數位類比轉換器," 系統晶片, pp. 83-87, 2007.
[46] M. Albiol, J. L. Gonzalez, and E. Alarcon, "Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 1, pp. 159-169, Apr. 2004.
[47] 蔡宗諺, "12位元500百萬赫芝電流式互補式金氧化半導體," 碩士, 電信工程系所, 國立交通大學, 新竹市, 2006.
[48] D. Lee, T. Kuo, and K. Wen, "Low-Cost 14-Bit Current-Steering DAC With a Randomized Thermometer-Coding Method," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 2, pp. 137-141, Feb. 2009.
[49] P. R. Kinget, "Device mismatch and tradeoffs in the design of analog circuits," IEEE Journal of Solid-State Circuits, vol. 40, no. 6, pp. 1212-1224, Jun. 2005.
[50] C. Yonghua and R. L. Geiger, "Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 7, pp. 585-595, Jul. 2000.
[51] P. E. Allen and D. R. Holberg, CMOS analog circuit design. New Delhi, India: Oxford University Press (in English), 2016.
[52] R. J. Baker, E. Institute of, and E. Electronics, CMOS circuit design, layout, and simulation. (in English), 2019.
[53] D. Hilbiber, "A new semiconductor voltage standard," in 1964 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 19-21 Feb. 1964 1964, vol. VII, pp. 32-33.
[54] R. J. Widlar, "New developments in IC voltage regulators," IEEE Journal of Solid-State Circuits, vol. 6, no. 1, pp. 2-7, Feb. 1971.
[55] K. E. Kuijk, "A precision reference voltage source," IEEE Journal of Solid-State Circuits, vol. 8, no. 3, pp. 222-226, Jun. 1973.
[56] C. J. B. Fayomi, G. I. Wirth, H. F. Achigui, and A. Matsuzawa, "Sub 1 V CMOS bandgap reference design techniques: a survey," Analog Integrated Circuits and Signal Processing, vol. 62, no. 2, pp. 141-157, 2010/02/01 2010.
[57] X. Li, Q. Wei, Z. Xu, J. Liu, H. Wang, and H. Yang, "A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 61, no. 8, pp. 2337-2347, Aug. 2014.
[58] Y. Tang et al., "A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping," IEEE Journal of Solid-State Circuits, vol. 46, no. 6, pp. 1371-1381, Jun. 2011.
[59] W. Tseng, C. Fan, and J. Wu, "A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With >70 dB SFDR up to 500 MHz," IEEE Journal of Solid-State Circuits, vol. 46, no. 12, pp. 2845-2856, Dec. 2011.
[60] W. Lin and T. Kuo, "A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection," IEEE Journal of Solid-State Circuits, vol. 47, no. 2, pp. 444-453, Feb. 2012.
[61] W. Lin, H. Huang, and T. Kuo, "A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < –61dB at 2.8 GS/s With DEMDRZ Technique," IEEE Journal of Solid-State Circuits, vol. 49, no. 3, pp. 708-717, Mar. 2014.
[62] H. Y. Huang, X. Y. Chen, and T. H. Kuo, "A 10-GS/s NRZ/Mixing DAC With Switching-Glitch Compensation Achieving SFDR > 64/50 dBc Over the First/Second Nyquist Zone," IEEE Journal of Solid-State Circuits, pp. 1-1, May 2021.
[63] H. Y. Huang and T. H. Kuo, "A 0.07-mm2 162-mW DAC Achieving >65 dBc SFDR and < −70 dBc IM3 at 10 GS/s With Output Impedance Compensation and Concentric Parallelogram Routing," IEEE Journal of Solid-State Circuits, vol. 55, no. 9, pp. 2478-2488, Sep. 2020.