超高精度的轉換器向來都極具市場重要性，但卻是相當難以設計的標的，需要極為審慎地處理製程變異所產生的系統性不匹配（Systematic Mismatch）與隨機性不匹配（Random Mismatch），方能成事。隨機性不匹配可以透過加大關鍵元件面積來抑制，但是系統性不匹配則須透過電路校準或精巧佈局才有可能解決。在數位至類比轉換器方面，西元1999 年有論文提出Q2 隨機漫步（Quad-Quad Random Walk）的佈局樣式，為14 位元轉換器成功立下小於0.3 LSB 積分非線性誤差（INL）的成就，迄今已近二十年，尚無人可以打破該精度的歷史紀錄！
本論文採用分段電流導向式(Segmented Current Steering)的架構，對線性度影響至鉅的高位元部分透過單位電流源矩陣來實現，主要是改造Random Walk 的概念來產生兩個子母矩陣，讓編號相連的元件儘量不相鄰，再透過子母矩陣相互嵌套成為初始佈局矩陣來大幅打亂相鄰電流源間的依存性，讓差分非線性誤差(DNL)趨近亂數化，以避免積分非線性誤差的累積。而後透過改良式Quad-Quad 的旋轉與鏡射(Mirroring)將此初始佈局矩陣複製16 份、均勻分佈在最終佈局大矩陣內，讓每個單位電流源皆由16個子電流源並聯而成，且該 16 個子電流源總共散佈在8個不同的x 座標與8個不同的y 座標上，使均勻度更甚以往，以打破14 位元數位至類比轉換器之歷史精度鴻溝與紀錄。
研究透過MATLAB 模擬製程變異下的INL，不論是拿Enhanced Q2 取代Q2、或是拿Random Pattern 來取代Random Walk，都可以獲致較好的INL，要是兩種技巧都以我們所發明者取代，可以發現Enhanced Q2 Random Pattern 的線性誤差比Q2Random Walk 平均小上6.07 倍，其有效位元數平均可以提高多達2.5 位元，紮實地證明所發明之Enhanced Q2 與Random Pattern 雙雙確實優於以往之Q2 與Random Walk。相關概念已與本校電機系方劭云教授的研究團隊合作，透過操控EDA 軟體來自動合成此電流源矩陣並以 MATLAB 行為模擬驗證其優秀精度。不過這僅僅是該些創新發明的觀念驗證，故本論文希望藉由獨創之嶄新佈局與電路設計一舉突破14 位元數位至類比轉換器之歷史精度水準，相關概念投稿至IEEE TCAD 並已被接受，即將刊登。

High accuracy data converters are always the hot spots of the application markets. However, they are really hard to design and engineers need to take a good care of the systematic and random mismatches of critical deices to achieve good enough accuracy. The random mismatch can be reduced by increasing the areas of critical devices. On the other hand, systematic mismatch can only be cancelled through circuit calibration or subtle layout patterns. For digital-to-analog converter (DAC), Q2 (Quad-Quad) Random Walk layout pattern was created in 1999 to achieve 0.3 LSB integral nonlinearity (INL) with 14-bit resolution. For more than 20 years till now, no designer on earth is capable of breaking this historical record in DAC accuracy.
A segmented matrix style current-steering DAC is proposed in this thesis. To enhance the linearity of Random Walk, Random Pattern is created to further randomize the positions among sequential current sources and thus minimize the correlations among their DNLs to prevent INL error accumulation. The mirroring and rotation of Quad-Quad are also modified to distribute the 16 sub-cells of each unary current sources into 8 x coordinates and 8 y coordinates instead of only 4 x coordinates and 8 y coordinates to get better uniformity.
Through MATLAB behavior simulations, the INL is reduced by replacing either Q2 with Enhanced Q2 or Random Walk with Random Pattern. On average, the INL of Enhanced Q2 Random Pattern is reduced from Q2 Random Walk by 6.07 times to increase almost 2.5 bits in the effective number of bits (ENOB). It thus proves the effectiveness and excellence of the proposed layout pattern. For implementation, some script and constraints are composed by Prof. Shao-Yun Fang and her Ph.D. student to guide the EDA tool for Automatic Placement and Routing (APR) according to the new matrix style layout pattern. The post simulations show that the proposed Enhanced Q2 Random Pattern is much better than the traditional Q2 Random Walk in accuracy. The idea was submitted to the top CAD journal, IEEE Transactions on Computer-Aided Design, and the paper was accepted already for future publication.

[1].David Marche, Yvon Savaria, and Yves Gagnon, “Laser Fine-Tuneable Deep-Submicrometer CMOS 14-bit DAC,” IEEE Trans. on Circuits and Systems I, vol. 55, no. 8, September. 2008.
[2].A. V. den Bosch, M. A. F. Borremans, M. S. J. Steyaert, and W. Sansen, “A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 315–324, Mar. 2001.
[3].B. Schafferer and R. Adams, “A 3 V CMOS 400 mW 14 b 1.4 GS/s DAC for multi-carrier applications,” in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 360–362.
[4].K. Doris, J. Briaire, D. Leenaerts, M. Vertregt, and A. van Roermund, “A 12 b 500 MS/s dac with > 70 dB SFDR up to 120 MHz in 0.18 µm CMOS,” in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 116–117.
[5].B. Jewett, J. Liu, and K. Poulton, “A 1.2 GS/s 15 b DAC for precision signal generation,” in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 110–112.
[6].G.A. M. Van Der Plas, J. Vandenbussche, W. Sansen, M. S. J. Steyaert, and G. G. E. Gielen, “A 14-bit intrinsic accuracy Q2 random walk CMOS DAC,” IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1708-1718, Dec. 1999.
[7].H. Samueli, “Broadband communications ICs: Enabling high-bandwidth connectivity in the home and office,” in Proc. IEEE 1999 ISSCC, Feb.1999, pp. 26–30.
[8].J. Bastos, M. Steyaert, and W. Sansen, “A high yield 12-bit 250-MS/s CMOS D/A converter,” in Proc. IEEE 1996 CICC, May 1996, pp.431–434.
[9].C-H. Lin and K. Bult, “A 10b 500 MSamples/s CMOS DAC in 0.6 mm2,” IEEE J. Solid-State Circuits, vol. 33, pp. 1948–1958, Dec. 1998.
[10].J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, “A 12-bit intrinisic accuracy high-speed CMOS DAC,” IEEE J. Solid-State Circuits, vol. 33, pp. 1959–1969, Dec. 1998.
 
[11].Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, “A 10-b 70-MS/s CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 26,pp. 637–642, Apr. 1991.
[12].T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba,“An 80-MHz 8-bit CMOS D/A converter,” IEEE J. Solid-State Circuits,vol. SC-21, pp. 983–988, Dec. 1986.
[13].A. R. Bugeja, B.-S. Song, P. L. Rakers, and S. F. Gillig, “A 14b 100MSample/s CMOS DAC designed for spectral performance,” in Proc. IEEE 1999 ISSCC, Feb. 1999, pp. 148–149.
[14].Y. Cong and R. L. Geiger, “A 1.5 V 14b 100MS/s self-calibrated DAC,” Proc. IEEE ISSCC Dig. Tech, Feb.2003, pp.128-129
[15].Jurgen Deveugele, Member, “A 10-bit 250-MS/s Binary-Weighted Current-Steering DAC, ” IEEE J. Solid-State Circuits, vol. 41, NO.2, February 2006.
[16].T. Chen and G. G. E. Giele, “A 14-bit 200-MHz current-steering DAC with switching-sequence post-adjustment calibration,” IEEE J. Solid-state Circuits, col. 42, no. 11, pp.2386-2394, Nov. 2007.
[17].Renzhi Liu, Student Member, “Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC,” IEEE Transactions on Circuits and Systems П, vol. 62,NO. 7,July 2015.
[18].A. Hastings, “The art of analog layout,” Prentice Hall, 2006.
[19].M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “ Matching Properties of MOS Transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989.
[20].B. Razavi, “Principles of Data Conversion System Design,” New York, Wiley-IEEE Press, 1994.
[21].Tony Chan Carusone, David A. Johns, and Kenneth W. Martin, “Analog Integrated Circuit Design 2/E,” John Wiley, 2012.
[22].A. S. Sedra and K. C. Smith, “Microelectronic Circuits,” 4th. Ed., Oxford University Press, 1998.
[23].U-K Moon, J. Silva, J. Steensgaard, and G. C. Temes, “A switched capacitor DAC with analog mismatch correction,” Proc. IEEE International Symposium on Circuits and Systems, vol. 4, pp.421–424, May 2000.
[24].A. Van den Bosch, M. Steyaert, and W. Sansen, “An accurate statistical yield model for CMOS current-steering D/A converter,” IEEE Int. Symp. on Circuit and Systems （ISCAS） , vol. 4, pp. IV.105-IV.108, May 2000.
[25].K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, “Characterisation and Modeling of Mismatch in MOS Transistors for Precision Analog Design, ” IEEE J. Solid-State Circuits, vol.21, no. 6, pp. 1057-1066, Dec. 1986.
[26].J. Bastos, M. S. J. Steyaert, A. Pergoot, and W. M. Sansen, “Influence of Die Attachment on MOS Transistor Matching, ”IEEE Trans. on Semiconductor Manufacturing, vol. 10, no. 2, pp. 209-218, May 1997.
[27].Xin Dai, Chengming He, Hanqing Xing, Degang Chen, and R. Geiger, “ An Nth order Central Symmetrical Layout Pattern for Nonlinear Gradients Cancellation, ” IEEE Int. Symp. on Circuit and Systems （ISCAS）, pp. 4835-4838, May 2005.
[28].A. Van den Bosch, M. Steyaert, and W. Sansen, “SFDR-bandwidth limitations for high-speed high-resolution current-steering CMOS D/A converters,” IEEE Int. Conf. Electronics on Circuits and Systems （ICECS）, vol. 3, pp. 1193-1196, Sept. 1999.
[29].K. O'Sullivan, C. Gorman, M. Hennessy, V. Callaghan, “A 12-bit 320-MSample/s current-steering CMOS D/A converter in 0.44 mm2”, IEEE Journal of Solid-State Circuits, vol.39, pp. 1064-1072, 2004.
[30].J. Bastos, A.M. Marques, M. S. J. Steyaert, and W. Sansen, “A 12-bit Intrinsic Accuracy High-Speed CMOS DAC, ” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1998.
[31].Chi-Hung Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2, ” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1948-1958, Dec. 1998.
[32]. 蔡宗彥(2006)。《A 12-bit 500-MSamples/s Current-steering CMOS D/A Converter》。交通大學碩士論文，新竹市。
[33].M. Albiol, J. L. Gonzalez, and E. Alarcon, “Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, pp. 159-169, 2004.
[34].B. Razavi, ”Design of analog CMOS integrated circuits, “Mc Graw-Hill College, 2002.
[35].Shantanu Gupta, Vishal Saxena, Kristy A. Campbell, and R. Jacob Baker, “ W-2W Current Steering DAC for Programming Phase Change Memory, ” IEEE Workshop on Microelectronics and Electron Devices, pp.1-4, Apr. 2009.
[36].Chueh-Hao Yu, Ching-Hsuan Hsieh, Tim-Kuei Shia, and Wen-Tzao Chen, “A 90nm 10-Bit 1GS/s Current-Steering DAC with 1-V Supply Voltage, ” IEEE Int. Symp. on Design, Automation, and Test (VLSI-DAT), pp. 255-258, Apr. 2008.
[37].D. Xin, H. Chengming, X. Hanqing, C. Degang, and R. Geiger, "An Nth order central symmetrical layout pattern for nonlinear gradients cancellation," in 2005 IEEE International Symposium on Circuits and Systems, 2005, pp. 4835-4838 Vol. 5.
[38].Manoj Kumar, Sandeep K. Arya, and Sujata Pandey, “Level Shifter Design for Low Power Applications,” International Journal of Computer Science & Information Technology, vol. 2, no. 5, Oct. 2010.
[39].Yunhua Yu, Haitao Shi, and Weining Ni, “An I/Q channel 12-bit 200MS/s CMOS DAC with three stage decoders for wireless communication, ” IEEE Int.Conf. on Wireless Communications & Signal Processing (WCSP), pp. 1-4, Nov. 2009.
[40].Jen-Huan Tsai, Yen-Ju Chen, Yan-Fong Lai, Meng-Hung Shen, and Po-Chiun Huang, “A 14-bit 200MS/s Current-Steering DAC Achieving over 82dB SFDR with Digitally-Assisted Calibration and Dynamic Matching Technique, ” IEEE Int. Symp. on Design, Automation, and Test （VLSI-DAT）, pp. 1-4, Apr. 2012.
[41].Xueqing Li, Qi Wei, Zhen Xu, Jianan Liu, Hui Wang, and Huazhong Yang, “A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ, ”IEEE Trans. on Circuits and Systems I, vol. 61, no. 8, pp. 2337-2347, Aug. 2014.
[42].Yongjion Tang, Joost Briaire, Kostas Doris, Robert van Veldhoven, Pieter C. W. van Beek, Hans Johannes A. Hegt, and Arthur H. M. van Roermund, “A 14 bit 200 MS/s DAC With SFDR > 78 dBc, IM3 < -83 dBc and NSD < -163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping,” IEEE J. Solid-State Circuits, vol. 46, no. 6, pp. 1371-1381, Apr. 2011.
[43].T.-C. Yu, S.-Y. Fang, C.-C. Chen, Y. Sun, and P. Chen, “Device Array Layout Synthesis with Nonlinear Gradient Compensation for a High-Accuracy Current-Steering DAC,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), accepted.