本研究針對不同IC長寬比(L/W ratio)及入力端與出力端金凸塊面積比(I/O ratio)的設計，探討COG壓著製程時，因IC大小及凸塊設計而影響膠材流動情形，進而使IC上各位置導電粒子變形程度產生不同的變化，而影響其導通阻抗。並利用波式和二項式統計理論探討各不同IC設計形成開路(open)機率，並使用三維短路(short) 機率統計計算短路產生的機率，以估計在TFT-LCD顯示器可能產生不良的比例。並利用有限元素分析方式模擬研究各種不同IC金凸塊上應力分布情形，找出影響模擬因子，以便未來利用模擬方式找出較佳的IC設計。而不同金凸塊硬度及所使用的壓著壓力參數都會影響導電粒子壓著變形狀態，因此針對凸塊硬度與使用壓著壓力研究導電粒子變形及導通阻抗關係。藉由此研究，找出較佳的IC設計及使用適當的凸塊硬度及其對應的壓著參數條件，未來可利用有限元素分析方式，加速IC設計評估，縮短開發時程並降低開發成本。

This paper investigates the interconnection between the driver IC and glass substrate via ACF of COG package. Several types of driver ICs with different bump area ratios (total input bump area/ total output bump area, I/O ratio) and length/width (L/W) ratios are designed in this experiment. The bump layout and the the driver IC design influence the adhesive flow in the bonding process, and the conductive particle deformation is influencd by the driver IC design. Better connection reliability can be achieved if more conductive particles remain on the bump with particles rarely clustered in the space between the bumps. The open connection probability estimation established the analytical model, and the Poisson and Binominal distribution are applied to estimate the open probability. The short probability model is also applied the statistical calculation of conductive particles connecting in a chain between the bumps. The three dimension space model equation is an extension from the one dimension space model which divided the volume between the bumps into cubic space with the same particle diameter length. The short probability model is related to the conductive particle density and distribution in the space after the bumps and glass substrate are connected, and it could estimate the defect ratio of the product.
The finite element method (FEM) is one of the most popular tools for stress and deformation testing in electronic packaging. The conductive particles are deformed using applied force that transfers to the gold bumps. Non-uniform force distribution on the IC bumps produces unbalanced stress distribution on bumps. Some conductive particles on the partial bumps are well deformed, while others are not. To investigate the stress distribution on the driver IC bumps, the COG packaging is modeled using ABAQUS 3-D FEM model in this analysis. The driver IC stress simulation tool could shorten the product development time and reduce the development cost in the LCD design industry. The bump hardness is alos a factor to influence the conductive particle deformation. The study provides guidance in bump design for driver ICs in the COG process.

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