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研究生: 陳豌蔚
Wan-Wei Chen
論文名稱: 細間距球柵陣列封裝繞線友善之導通孔配置技術
Routing Friendly Via Assignment for Fine Pitch Ball Grid Array Package Design
指導教授: 劉一宇
Yi-Yu Liu
口試委員: 方劭云
王國華
陳勇志
學位類別: 碩士
Master
系所名稱: 電資學院 - 資訊工程系
Department of Computer Science and Information Engineering
論文出版年: 2020
畢業學年度: 108
語文別: 英文
論文頁數: 55
中文關鍵詞: 導通孔分配封裝細間距球柵陣列整數線性規劃
外文關鍵詞: FBGA, Package, ILP, Via assignment
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基板在晶片封裝中是一個極為重要的載體,隨著半導體產品的需求快速成長,基板市場將越來越重要。細間距球柵陣列為小型電子設備提供更多的輸入輸出腳位,因此被廣泛使用。一般而言,由於基板是通過機械工藝製成,不協調的導通孔(via)尺寸的問題會影響可繞線性。此外,引腳(finger)和凸塊(bump ball)是障礙物,並且不利地影響繞線資源。基板繞線必須在緊縮的資源中不違反任何設計規則完成, 因此增加了設計複雜度。在本文中,我們對於兩層的細間距球柵陣列封裝提出基於整數線性規劃的導通孔配置技術。在繞線友善導通孔配置的前提下,我們的方法最大化預先擺放的導通孔位置數量,將之作為全局布線器的初始。實驗結果表明我們的方法可以有效提高繞線質量和運行時間。


IC substrate is a significant carrier in chip package. As the demand for semiconductor products grows rapidly, the substrate market will be more and more important. Fine pitch ball grid array (FBGA) provides more I/O pin counts for small electronic devices. Therefore, it is widely used in highly integrated package designs. In general, package substrates are manufactured through mechanical processes, mismatched via-hole dimension problems could impact the routability. In addition, fingers and bump balls are routing obstacles and affect routing resource adversely. The substrate routing must be completed without any design rule constraint (DRC) violations in a tightly resource-constrained region. Therefore, the design complexity is increased. In this thesis, we propose an ILP-based via assignment method for 2-layer fine pitch ball grid array package. Under the premise of routing friendly via assignment, our method maximizes the number of pre-placed via positions for global router to start with. global router to start with. Experimental results demonstrate that our method effectively improves both the routing quality and run time.

ABSTRACT v List of Tables ix List of Figures x CHAPTER 1. Introduction 1.1 BGA Bonding Types 1.2 Package Substrate Routing 1.3 Motivation CHAPTER 2. Preliminaries 2.1 Previous Works 2.2 Minimum-cost Multiple-commodity Flow Model 2.3 Problem Formulation CHAPTER 3. Proposed Methodology 3.1 Algorithm Overview 3.2 Sector Partition 3.3 Constraints and Objective 3.3.1 Net Constraint 3.3.2 Via Candidate Constraint 3.3.3 Crossing Constraint 3.3.4 Row Sequence Constraint 3.3.5 Conflict Constraint 3.3.6 Adjacent Via Constraint 3.3.7 Finger Constraint 3.3.8 Capacity Constraint 3.3.9 Objective Function 3.4 Constraint Refinement and Reduction 3.4.1 Optimized Adjacent Via Constraint 3.4.2 Capacity Constraint Reduction 3.4.3 Restricted Via Candidate CHAPTER 4. Experimental Results CHAPTER 5. Conclusions Bibliography

[1] PCBCART https://www.pcbcart.com/article/content/ic-substrate-pcb.html
[2] MoneyDJ https://www.moneydj.com/KMDJ/wiki/wikiViewer.aspx?keyid=10e8bdb1-
5811-4f9d-b837-207d12cec830.
[3] Lee Levine, "Wire Bonding," ASM International, 2016.
[4] Chi-An Pan, "Integer Linear Programming Based Substrate Routing Framework for Fine Pitch Ball Grid Array Package," M. S. thesis, National Taiwan University of Science and Technology, Taipei, Taiwan, 2019.
[5] J. Shibata, M. Horita, N. Izumi, T. Shikano, M. Okada, Y. Noguchi, K. Imamura, H. Fukunaga, M. Yasunaga, T. Hirai, T. Hashimoto, Y. Takemoto, "Development of Fine Pitch Ball Grid Array," IEEE 2nd 1998 IEMT/IMC Symposium, pp.45-49, 1998.
[6] Design guide for semiconductor packages Fine-pitch Ball Grid Array and Fine pitch Land Grid Array (FBGA/FLGA), Standard of Japan Electronics and Information Technology Industries Association.
[7] Design Guidelines for Cypress Ball Grid Array (BGA) Packaged Devices, https://www.cypress.com/.
[8] T. Yan, M. D. Wong, "Recent Research Development In PCB Layout ," International Conference on Computer-Aided Design (ICCAD), pp. 398-403, 2010.
[9] Farhang Yazdani, "Foundations of Heterogeneous Integration: An Industry-
Based, 2.5D/3D Path nding and Co-Design Approach," Springer International Publishing AG, 2018.
[10] Y. Kubo, A. Takahashi, "A Global Routing Method for 2-Layer Ball Grid Array
Packages," in Proc. ISPD, pp.36-43, 2005.
[11] Y. Tomioka, A. Takahashi, "Routability Driven Modi cation Method of Monotonic Via Assignment for 2-layer Ball Grid Array Packages," in Proc. ASPDAC, pp.238-243, 2008.
[12] Y. Tomioka, A. Takahashi, "Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages,"IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, vol.E92-A, no.6, pp.1433-1441, 2009.
[13] Y. Tomioka, Y. Kurata, Y. Kohira, A. Takahashi, "MILP-Based Ecient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages," IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, vol.E92-A, no.12, pp.2998-3006, 2009.
[14] F. Jiao, S. Dong, "Ordered Escape routing for grid pin array based on Min-cost
Multi-commodity Flow," in Proc. ASPDAC, pp.384-389, 2016.
[15] X. Jia, Y. Cai, Q. Zhou, B. Yu, "A Multicommodity Flow-Based Detailed Router With Ecient Acceleration Techniques," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.217-230, vol.37, i.1, Jan. 2018.
[16] Jun-Sheng Wu, "Optimization strategies for integer linear programming based
ball grid array substrate router," M. S. thesis, National Taiwan University of Science and Technology, Taipei, Taiwan, 2019.
[17] Gurobi Optimizer 8.1 https://www.gurobi.com/.
[18] Cadence Allegro Package Designer 16.6 https://www.cadence.com/.

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