許多附有快速鎖定功能全數位式鎖相迴路(all-digital phase-locked loop)在過去被提出，但往往都是花大面積與高功耗去達成。而在終端裝置應用中，要求嵌入式系統低功率和低成本，但也需要快速鎖定功，以便微控制器可以從睡眠模式快速喚醒。
本論文提出了一個適用於微控制器之時脈產生器全數位式鎖相迴路。一個由多工器鏈組成的數位控制振盪器(digitally controlled oscillator)設計為兩種模式：振盪模式和時間數位轉換模式。因此，DCO可在一開始時用來量測輸入頻率，改善鎖定時間，之後再作為振盪器運作。藉由重複利用延遲線，此全數位式鎖相迴路可以以較小的面積實現更快的鎖定時間。本論文也提出了依FPGA架構特性所實現之細調延遲單元，最高可在FPGA上達到0.137 ns解析度。
本論文提出全數位式鎖相迴路在Xilinx Virtex-5 V5LX110T上實現，使用LUTs(lookup table) 471個、暫存器179個，輸出範圍為8.22MHz-78MHz，可在十個週期內進入鎖定狀態。輸出頻率為75 MHz時，峰峰值抖動為0.154ns。

A lot of fast-lock-in all-digital phase-locked loops (ADPLL) have been proposed, but they usually come with large area cost and power consumption. For those low-end sensor devices, low-power and low-cost ADPLLs are required. A fast-lock-in feature is also desired so that microcontroller can wake up quickly from sleep mode to run mode.
In this thesis, a complete all-digital phase-locked loop for clock generation is proposed. A multiplexer-chain-based digitally controlled oscillator (DCO) is designed into two modes: the oscillating mode and the time-to-digital conversion (TDC) mode.
Hence the DCO can be used to capture the input frequency at the beginning to improve lock-in time and then work as oscillator later. As a consequence, the ADPLL can achieve faster lock-in time at a small cost by reusing the delay line. This thesis also proposes a fine-tuning delay cell made of FPGA primitives in which it can achieve 0.137-ns resolution on FPGA.
The proposed ADPLL is implemented on Xilinx Virtex-5 V5LX110T. It uses 471 LUTs and 179 registers. The ADPLL output range is from 8.22 MHz to 78 MHz and can enter lock-in status within ten cycles. The peak-to-peak jitter is 0.154 ns with the output frequency of 75 MHz.

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