本論文提出一個實現於現場可程式化閘陣列(Field Programmable Gate Array, FPGA)並利用延遲迴繞法為基礎的時間至數位轉換電路(Time-to-digital converter, TDC)。本論文提出之時間至數位轉換電路不但可以抑制溫度變異，並達到極高解析度。利用FPGA內建之延遲元件，讓參考時脈衝經過逐級延遲，利用延遲迴繞(Wrapping)效果讓所有延遲脈衝之相位分布在0~360度之參考週期內，並透過靜態時序分析，以排序挑出最接近理想之延遲週期，藉以降低量化誤差、進而達到高解析度。其解析度可高達1ps，且不隨溫度變異而改變，另外加入了偏移校準技術以更進一步的抑制溫度變異對偏移量的影響，並且將輸出偏移誤差抑制在10個LSB之內。長線量測之積分非線性誤差(INL)為-2.09~2.36 LSB、差分非線性誤差(DNL)為-1.45~1.73LSB。並完整測試涵蓋0度到50度的運作功能，成功驗證本時間至數位轉換電路抑制溫度變異之優異效果，整體效能甚至優於大部分的全客戶(Full Custom)設計之版本。

A high resolution FPGA time-to-digital converter based on delay wrapping and phase sorting to achieve an extremely fine resolution of 1ps is proposed in this thesis. A single clock passed a series of delay elements is used to generate multiple reference clocks with different delays. Due to periodicity, those delays will be equivalently warpped between 0~360 and then phase sorting is applied to select proper reference clocks with delays uniformly distributed over 0~360 based on the required solution to achieve the best linearity. Furthermore, to reduce the impact of temperature-sensitive the offset, a cancellation circuit is created to substantially reduce offset and confine the output difference within 10LSB for the same input interval. With 1ps such a fine resolution, the long-term integral nonlinearity (INL) is measured to be merely -2.09~2.36 LSB and the corresponding differential nonlinearity (DNL) is -1.45~1.73LSB. This TDC was tested to be fully functional over 0C to 50C ambient temperature range with extremely low resolution variations. Its performance is even much superior than most full-custom design TDCs.

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