近年來，以鎖相迴路為主的頻率合成器大量被使用在無線通訊系統中。相對地，各式各樣的頻率合成器就被研發出來。本論文採用TSMC 0.18 um CMOS製程來實現頻段為2.4 GHz全數位之頻率合成器，其中電路採用兩段式時間至數位轉換器，目的為提高時間至數位轉換器之解析度，以改善整體頻率合成器的頻帶內雜訊。

時間至數位轉換器採用延遲線架構，優點為可操作於高速，但此架構解析度受限於單一延遲元件，故解析度無法達到非常精細;若使用游標卡尺式，可達到極高的解析度，但取樣頻率會受到限制，無法操作在高速系統。此論文採用的數位至時間轉換器亦可改善解析度與取樣頻率之間做取捨的關係，進而可達到高速度以及高解析度的優點，提供給頻率合成器使用，最後以達成低相位雜訊、面積小、高解析度以及快速鎖定之優點。

本電路在數位電路直流供給電壓1.8 V及類比電路直流供給電壓1.2 V下，量測結果顯示，中心頻率為2.37 GHz時，輸出信號功率為-6.82 dBm，鎖定時之相位雜訊為-115.89 dBc/Hz@1 MHz，功耗為12.9 mW，晶片面積為0.79 × 0.79 mm2。

In recent years, PLL-based frequency synthesizers are widely used in wireless communication systems, and various frequency synthesizers have been developed relatively. This thesis adopts TSMC 0.18 um CMOS processing to realize an all-digital frequency synthesizer of 2.4 GHz band, wherein the circuit adopts a two-step time-to-digital converter (TDC) which aims at improving the time resolution, so as to reduce the in-band phase noise within the band of the frequency synthesizer in general.

The TDC adopts gate delay line structure, which can operate in high speed. This type TDC time resolution is limited by the gate delay value, so it is hard to achieve high time resolution. Another TDC is the vernier delay line structure, which inherently has a high time resolution, but this structure cannot operate in high speed system. This proposed TDC, which can improve the alternative relationship between time resolution and sampling rate, so as to realize the high speed and high resolution property of the frequency synthesizers to finally achieve lower phase noise, smaller area, higher resolution and rapid locking.

The digital circuit is supplied with 1.8 V DC while the analog circuit is supplied with 1.2 V DC. The measuring result shows that when center frequency is 2.37 GHz, the output signal power will be -6.82 dBm. After it has been locked, the phase noise is -115.89 dBc/Hz@1 MHz and the power consumption is 12.9 mW, while the chip area is 0.79 × 0.79 mm2.

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