以故障分散技術提升非揮發性記憶體的可靠度與良率｜國立臺灣科技大學博碩士論文系統

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研究生：	鄭浩晟 Hao-cheng Jheng
論文名稱：	以故障分散技術提升非揮發性記憶體的可靠度與良率 Fault Scrambling Techniques for Reliability and Yield Enhancement of Non-Volatile Memories
指導教授：	呂學坤 Shyue-kung Lu
口試委員:	郭斯彥 Sy-yen Kuo 李進福 Jin-fu Li 洪進華 Jin-hua Hong 陳俊良 Jiann-liang Chen
學位類別：	碩士 Master
系所名稱：	電資學院 - 電機工程系 Department of Electrical Engineering
論文出版年：	2013
畢業學年度：	101
語文別：	英文
論文頁數：	80
中文關鍵詞：	可靠度、良率、非揮發性記憶體、故障分散
外文關鍵詞：	Reliability, Yield, Non-Volatile Memories, Scrambling
相關次數：	點閱：201 下載：9
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針對記憶體中的故障細胞，除了只使用備用行或備用列來取代之外，錯誤更正碼也被認為是一種有效率的修復技術。錯誤更正碼若被用來處理永久性的故障 (Permanent Faults)，記憶體在製程上的良率與可靠度都能得到提升。但是，一旦一個編碼字 (Codeword) 當中的故障位元數超過一個時，廣泛被使用的單錯更正雙錯偵測 (Single-Error Correction and Double-Error Detection) 碼的保護能力將會因此受到限制。因此，為了解決這種困境，這篇論文將提出一個有效的故障分散技術 (Fault Scrambling Techniques)。有別於在傳統的故障偵測與更正 (Error Detection and Correction) 架構中，由固定的記憶體細胞以組成一個編碼字，我們將嘗試重組一個編碼字中的記憶體細胞使得每一個編碼字最多只含有一個故障細胞。我們也提出相對應的雜散電路 (Scrambling Circuits) ，此外，我們也開發了用來估算修復率與硬體成本的模擬器。根據實驗數據顯示，在幾乎可以忽略的硬體成本之下，修復率將有很顯著的改善。

Instead of merely using redundant rows/columns to replace faulty cells, error-correcting codes are also considered an effective technique to cure permanent faults for the enhancement of fabrication yield and reliability of memories. However, if the number of faulty bits in a codeword is greater than 1, the protection capability of the widely used SEC-DED (single-error correction and double-error detection) codes will be limited. In order to cure this dilemma, efficient fault scrambling techniques are proposed in this thesis. Unlike the fixed constituting memory cells of a codeword in the conventional EDAC (Error Detection and Correction) schemes, we try to refigure the constituent memory cells of codewords such that each codeword consists of at most one faulty cell. The corresponding scrambling circuits are also proposed and a simulator is developed to evaluate the repair rates and hardware overhead. According to experimental results, the repair rates can be improved significantly with negligible hardware overhead.

誌謝	I
摘要	II
Abstract	III
Contents	IV
List of Figures	VII
List of Tables	IX
Chapter 1	Introduction	1
1.1	Motivation and Background	1
1.2	Organization	4
Chapter 2	Review of Built-in Self-Test, Diagnosis and Repair Techniques	5
2.1	Fault Models and Test Algorithms	5
2.2	Built-In Self-Test	8
2.3	Built-In Self-Diagnosis	11
2.4	Built-In Self-Repair & Built-In Redundancy Analysis	12
Chapter 3	Review of Error Detection and Correction Codes	16
3.1	Fundamentals of Error Correction Codes	16
3.1.1	Hamming Code	18
3.1.2	Modified Hamming Code	19
3.1.3	Hsiao Code	20
3.2	The Conventional Fault-Tolerance Scheme Combining the Repair Redundancy and the ECC Schemes	21
Chapter 4	Fault Scrambling Technique for Reliability and Yield Enhancement	25
4.1	Memory Architectures	25
4.2	Fault Scrambling Techniques	29
4.2.1	Row Scrambling Technique	30
4.2.2	Column Scrambling Technique	30
4.2.3	Hybrid Scrambling Technique	32
4.2.4	Memory Architectures with the Fault Scrambling Techniques Incorporated	34
4.3	Test and Repair Flow with the Fault Scrambling Techniques	35
4.4	BIST Architecture for the Fault Scrambling Technique	39
4.5	An Example of Fault Scrambling Technique	41
Chapter 5	Experimental Results	50
5.1	Defect Distributions and Fault Models	50
5.2	Repair Rate Analysis	52
5.3	Area Overhead Analysis	57
Chapter 6    Conclusions and Future Works	61
6.1 Conclusions	61
6.2 Future Works	61
References	63

                                

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