隨著製程技術進入到VDSM (very deep sub-micro)，匯流排上的導線間距也隨之縮小，造成匯流排的耦合電容快速增長，所以對晶片上訊號傳送的可靠度與功率的消耗都有明顯的影響，因此設計出一個低功率消耗及高可靠度的匯流排確實有其需要，為此本論文提出一個藉由導線重排及額外空間配置的方法來建立一個低功率容錯匯流排。
本論文所提出的低功率容錯匯流排架構是以漢明碼的編碼為基礎，利用圖形理論在一多項式時間內，根據已知的資料流對導線作重排及非均勻空間的配置，藉此來降低容錯匯流排之間耦合電容的影響，另一方面此方法並不需要額外的編碼電路，因此並不會增加原本已具有編/解碼電路容錯匯流排的負擔而造成訊號的延遲。根據實驗結果的顯示本論文所提出的架構，當額外空間為20×dmin時最高可減少43%的功率消耗，而最少也可達到30%。

As technology scales to the very deep submicron (VDSM) dimensions, the coupling capacitances between adjacent bus wire grow rapidly, and have a significant impact on power consumption and signal integrity issue of whole chip. Thus, it is important to design fault-tolerant buses that dissipate less power and raise reliability without sacrificing performance.
In this paper, we address the problem of using Hamming single error correcting code by simultaneously optimizing wire permutation and spacing. We propose an efficient algorithm that use graph theory for this optimization problem in a polynomial time. Unlike previous study, our approach using in high bandwidth fault-tolerant buses can efficient reduce the coupling capacitances without more additional space.
For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs. The results show that our approach can save energy up to 43% for the best case, and 30% for the worst with 20×dmin additional width.

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