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研究生： 黃弘鈞
Hung-Chun HUANG
論文名稱： 低抖動鎖相迴路之電路設計與實現
Design and Implementation of Low Jitter Phase-Locked Loop Circuits
指導教授： 鍾勇輝
Yung-Hui Chung
口試委員: 姚嘉瑜
Chia-Yu Yao
陳筱青
Hsiao-Chin Chen
曾偉信
Wei-Hsin Tseng,
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2020
畢業學年度： 108
語文別： 中文
論文頁數： 77
中文關鍵詞： 鎖相迴路 、時脈產生器 、突波消除
外文關鍵詞： Phae-Locked-Loop, time generator, Spur Reduction
相關次數： 點閱：196  下載：5 
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    • 本篇論文研究提出了一種多相位低抖動鎖相迴路。並且為了防止由於輸出頻率引起的阻尼因數和迴路頻寬對輸入訊號比變化，鎖相迴路使用自偏壓技術來產生具有低抖動性能的8相位輸出，並以此提出三種架構來滿足多通道類比數位轉換器之應用，其輸出頻率範圍為80MHz至320MHz。 另外，為了避免將多相位高頻時鐘脈波直接輸出到晶片外部，本篇論文提出了一個抖動測試電路來精確測量僅由鎖相迴路產生的時鐘抖動。本篇論文的三個晶片實現皆使用0.18微米CMOS製程。
    第一個設計是使用自偏壓技術之鎖相迴路，晶片使用1.5V電源電壓，在160MHz時，功率消耗為4.2毫瓦，核心電路之面積為0.06平方毫米。在PLL輸出頻率為160 MHz時，量測的峰對峰值抖動約為87 ps。在使用抖動校正方程式後，測得的均方根抖動值約為7 ps。
    第二個設計是以第一個設計做衍生，使用注入式鎖定技術。在壓控振盪器注入一個乾淨的脈衝，來降低源自於壓控振盪器的抖動量。晶片使用1.5V電源電壓，在160MHz時，功率消耗為4.9毫瓦，核心電路之面積為0.08平方毫米。在PLL輸出頻率為160 MHz時，量測的峰對峰值抖動約為80 ps。在使用抖動校正方程式後，測得的均方根抖動值約為9 ps。
    第三個設計是將壓控震盪器之頻率提高至640M Hz，並在迴路中加入除頻電路以保持輸出頻率在160MHz。它是利用自偏壓鎖相迴路的特性，使鎖相迴路的抖動可以在壓控震盪器之頻率升高時而維持迴路特性不變，又可以將壓控震盪器貢獻的抖動量降低。電路使用1.5V電源電壓，在輸出頻率為160MHz時，功率消耗為22.3毫瓦，模擬的峰對峰值抖動約為13.1ps。

    This paper researches and proposes a multi-phase low jitter phase-locked loop. And to prevent the damping factor and loop bandwidth caused by the output frequency from changing to the input signal ratio, the phase-locked loop uses self-biasing technology to generate 8-phase output with low jitter performance, and proposes three architectures to meet the multi-channel analogy For digital converter applications, the output frequency range is from 80MHz to 320MHz. In addition, to avoid direct output of multi-phase high-frequency clock pulses to the outside of the chip, this paper proposes a jitter test circuit to accurately measure the clock jitter generated only by the phase-locked loop. The three chip implementations in this paper all use 0.18 micron CMOS process.
    The first design is a phase-locked loop using self-biasing technology. The chip uses a 1.5V power supply voltage. At 160MHz, the power consumption is 4.2 milliwatts and the core circuit area is 0.06 square millimeters. When the PLL output frequency is 160 MHz, the measured peak-to-peak jitter is about 87 ps. After using the jitter correction equation, the measured root-mean-square jitter value is about 7 ps.
    We derive the second design from the first design, using injection locking technology. Inject a clean pulse into the voltage-controlled oscillator to reduce the amount of jitter originating from the voltage-controlled oscillator. The chip uses a 1.5V power supply voltage, at 160MHz, the power consumption is 4.9 milliwatts, and the area of the core circuit is 0.08 square millimeters. When the PLL output frequency is 160 MHz, the measured peak-to-peak jitter is about 80 ps. After using the jitter correction equation, the measured root mean square jitter value is about 9 ps.
    The third design is to increase the frequency of the voltage-controlled oscillator to 640M Hz, and add a frequency divider circuit to the loop to keep the output frequency at 160MHz. It uses the characteristics of the self-biased phase-locked loop, so that the jitter of the phase-locked loop can maintain the loop characteristics unchanged when the frequency of the voltage-controlled oscillator increases, and can reduce the amount of jitter contributed by the voltage-controlled oscillator. The circuit uses a 1.5V power supply voltage. When the output frequency is 160MHz, the power consumption is 22.3 milliwatts, and the simulated peak-to-peak jitter is about 13.1 ps.

    目錄 摘要 Abstract 致謝 圖目錄 表目錄 第1章 導論 1.1 研究動機 1.2 論文架構 第2章 自偏壓鎖相迴路 2.1 傳統鎖相迴路 2.2 自偏壓鎖相迴路架構 2.2.1 相位頻率檢測電路 (PFD) 2.2.2 零偏移電荷幫浦 2.2.3 自偏壓取樣前饋濾波器網絡 2.2.4 四階環形振盪器 2.2.5 差動轉換單端電路 2.3 多相位PLL抖動檢測電路 2.4 量測結果 2.5 結論 第3章 使用注入式鎖定技術之鎖相迴路 3.1 注入式鎖定技術 3.2 注入時間考量 3.3 脈衝產生器(Pulse Generator) 3.4 注入式環形振盪器 3.5 量測結果 3.6 結論 第4章 低抖動多相時鐘發生電路 4.1 低抖動多相時鐘發生電路架構 4.2 低抖動多相時鐘發生器個部位架構 4.2.1 相位頻率檢測器(PFD) 4.2.2 電流幫浦(CP) 4.2.3 電容切換電路 4.2.4 複製放大器 4.2.5 電壓控制震盪器 4.2.6 差動轉換單端電路 4.2.7 多相位PLL抖動檢測電路 4.3 注入式鎖相迴路部位架構 4.4 除頻器架構部分 4.5 模擬結果 第5章 結論與未來展望 5.1 結論 5.2 未來展望   圖目錄 圖1 1. 傳統鎖相迴路之方塊圖。 圖1 2. ADC的時脈抖動對應SNR的輸入頻率關係圖。 圖1 3.多相位低抖動鎖相迴路之架構圖。 圖2 1. 傳統鎖相迴路方塊圖。 圖2 2. 使用自偏壓技術的二階鎖相迴路[6]。 圖2 3. 迴路濾波電路之電阻轉換示意圖[6]。 圖2 4. 對稱性負載之實現[6]。 圖2 5. 自偏壓電路[6]。 圖2 6. 一階濾波器之抖動模式[1]。 圖2 7. 二階濾波器之抖動模式[1]。 圖2 8. 取樣前饋環路濾波器之抖動模式[1]。 圖2 9. 前饋濾波器網絡[1]。 圖 2 10. 穩定度模擬圖 圖2 11. 相位頻率檢測電路圖。 圖2 12. 相位頻率檢測電路之時序圖。 圖2 13. 相位頻率檢測器之相位雜訊圖 圖2 14. 電流幫浦之電路圖[2]。 圖2 15. 電流幫浦之相位雜訊頻譜圖。 圖2 16. 應用於自偏壓鎖相迴路之前饋濾波器電路[5]。 圖2 17. 迴路濾波器之相位雜訊頻譜圖。 圖2 18. 對稱性負載之延遲級[6]。 圖2 19. 環形振盪器之方塊圖。 圖 2 20. 環形振盪器之波形圖。 圖2 21. 環型振盪器(VCO)之(A)頻率對電壓之轉換曲線，(B)增益(KVCO) 圖2 22. 環型振盪器之相位雜訊頻譜圖 圖2 23. 單一的差動轉單端緩衝電路[6] 圖2 24. VCO的差動轉單端緩衝電路 圖2 25. PLL抖動檢測電路之方塊圖 圖2 26. PLL晶片布局圖 圖2 27. PLL晶片之照相圖 圖2 28. 抖動直方圖 圖2 29. PLL的功耗分布圖 圖2 30. 在不同輸出頻率下的PLL抖動量測結果 圖 2 31. VCO頻率與JITTER關係圖 圖 3 1. 常規注入鎖定鎖相迴路 圖 3 2. 注入相位校正示意圖 圖 3 3. 注入前後獨立VCO的輸入和輸出相位關係圖[18] 圖 3 4. (A)具有注入的VCO延遲級簡化半電路(B)通過脈衝電壓向量變化圖 圖 3 5. 注入時序 圖 3 6. 注入時間考量[26] 圖 3 7. 注入時間考量 圖 3 8. 脈衝產生器 圖 3 9. 注入式對稱負載延遲級 圖 3 10. 注入式環形振盪器迴路 圖3 11. 晶片布局圖 圖3 12. 裸晶照相圖 圖3 13. 抖動直方圖 圖3 14. 功率消耗圖 圖4 1. 低抖動多相位注入式鎖相迴路示意圖 圖 4 2. 低抖動多相時鐘發生器個部位架構圖 圖 4 3. 相位頻率檢測器電路圖 圖 4 4. 電流幫浦電路圖 圖 4 5. 電容切換電路圖 圖 4 6. 複製放大器電路圖 圖 4 7. 電壓控制震盪器電路圖 圖 4 8. 差動轉換單端電路圖 圖 4 9. 多相位PLL抖動檢測電路 圖 4 10. 脈衝產生器電路圖 圖4 11. 數位控制除頻器電路圖 圖4 12. 除頻器時序示意圖(A)未經過CK同步時序(B)經過CK同步後時序 圖 4 13. 前模擬輸出眼圖 圖 4 14. 功耗佔比 表目錄 表 2.1. 量測輸出抖動 表 2.2. 性能摘要與比較 表 2.3. PLL的功耗分布表 表3.1. 注入不同頻率對抖動影響 表3.2. SILPLL功率分布表 表 4.1. PFD 各元件大小 表 4.2. CP各元件大小 表 4.3. 電容切換電路各元件大小 表 4.4. 複製放大器各元件大小 表 4.5. 電壓控制震盪器各元件大小 表 4.6. 差動轉換單端電路各元件大小 表 4.7. 脈衝產生器電路各元件大小 *表 4.8. 輸出640MHZ 時RMS抖動量 *表 4.9. 輸出320MHZ 時RMS抖動量 *表 4.10. 輸出160MHZ 時RMS抖動量 表 5.1. VCO注入/非注入模擬結果

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