10.24 GHz 鎖相迴路晶片設計｜國立臺灣科技大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	林正宗 Cheng-Tsung Lin
論文名稱：	10.24 GHz 鎖相迴路晶片設計 10.24 GHz Phase-Locked Loop Chip Design
指導教授：	黃進芳 Jhin-Fang Huang 劉榮宜 Ron-Yi Liu
口試委員:	徐敬文 Ching-Wen Hsue 張勝良 Sheng-Lyang Jang 陳國龍 Gou-Long Chen
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2009
畢業學年度：	98
語文別：	英文
論文頁數：	83
中文關鍵詞：	鎖相迴路、相位/頻率鑑別器、壓控振盪器、除頻器、濾波器
外文關鍵詞：	Prescaler
相關次數：	點閱：239 下載：12
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

這篇論文提出一個高頻的鎖相迴路(PLL)分析和設計。電路使用TSMC CMOS 0.18μm 製程。然而電路的組成元件包括了有相位/頻率檢測器、電流幫浦、低通濾波器、除頻器和壓控振盪器。鎖相迴路採用一個高頻鎖相迴路的技術, 輸出頻率是10.24 GHz。LC VCO是使用一個NMOS耦合對的架構, 使用高Q值的對稱式中心抽頭電感以減少VCO在PLL中的面積。然而, 使得相位雜訊在1 MHz可以達到-106 dBc/Hz, 而整個鎖相迴路可以在小於20μs鎖住、功率消耗為43.67 mW, 晶片的面積為1.1x1.1mm2。
在設計的程序中包括了設計及模擬。PLL是一個很重要的設計因為它是一個脈波產生器和頻率合成器。脈波產生器產生數位脈波訊號和頻率產生器能夠藉由參考訊號產生不同的頻率。

This thesis presents the analysis and design of a high frequency phase-locked loop (PLL). The circuit has been fabricated using a TSMC CMOS 0.18μm process. These components consist of Phase Frequency Detector (PFD), charge pump (CP), low pass filter (LPF), frequency divider and the voltage controlled oscillator (VCO). The PLL frequency output signal at 10.24 GHz and is the high operational frequency PLL in the technology. A NMOS cross coupled pairs of the LC VCO with a center tapped inductor adopted to enhances the Q value and reduces the die area of PLL, thus makes the phase noise -106 dBc/Hz at 1 MHz, the locking time is about 20 μs and whole circuit power consumption is 43.67 mW. Also, the chip area occupies only 1.1x1.1mm2.
This design flow includes design and simulation of the components. The important function designing the PLL was a clock generator and frequency synthesizer. A clock generator generates a digital clock signal and a frequency synthesizer generates a frequency that can have a different frequency from the original reference signal.

致謝
中文摘要
Abstract
Contents
List of Figures
List of Tables
Chapter 1 Introduction
        1.1 Motivation
        1.2 Organization of Dissertation
Chapter 2 PLL-based Frequency Synthesizers
        2.1 Phase Noise and Spurious Tone
        2.2 Timing Jitter
        2.3 PLL-based Frequency Synthesizer
        2.3.1 Integer-N PLL Frequency Synthesizer
        2.3.2 Fractional-N Frequency Synthesizer
        2.3.3 Delay-Locked Loop Frequency Synthesizer
Chapter 3 Voltage Controlled Oscillator Design and Analysis
        3.1 Introduction
        3.2 LC Oscillator
        3.3 LC VCO Topologies
        3.4 VCO Figure of Merit
        3.5 LC VCO Phase Noise Model
        3.5.1 Leeson’s Model
        3.5.2 Hajimiri’s Non-linear time Variant Model
Chapter 4 Phase-Locked Loop Implementation
        4.1 Behavioral Simulation
        4.2 Phase Frequency Detector (PFD)
        4.3 Charge Pump (CP)
        4.4 Loop Filter
        4.5 Voltage Controlled Oscillator
        4.6 Frequency Divider
        4.6.1 Current Mode Logic (CML)
        4.6.2 True Single Phase Clock (TSPC) Divider
Chapter 5 Simulations Results and Measurement Setup
        5.1 Simulation Results
        5.2 Measurement Setup
Chapter 6 Conclusion
        6.1 Conclusion
        6.2 Future Work
Bibliography

                                

[1] B. Razavi, "A study of phase noise in CMOS oscillators," Solid-State Circuits, IEEE Journal of, vol. 31, pp. 331-343, 1996.
[2] K. Kishine, N. Ishihara, K. Takiguchi, and H. Ichino, "A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs," Solid-State Circuits, IEEE Journal of, vol. 34, pp. 805-812, 1999.
[3] G. Georgiou, Y. Baeyens, C. Young-Kai, A. H. Gnauck, C. Gropper, P. Paschke, R. Pullela, M. Reinhold, C. Dorschky, J. P. Mattia, T. W. von Mohrenfels, and C. Schulien, "Clock and data recovery IC for 40-Gb/s fiber-optic receiver," Solid-State Circuits, IEEE Journal of, vol. 37, pp. 1120-1125, 2002.
[4] F. Herzel and B. Razavi, "A study of oscillator jitter due to supply and substrate noise," Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 46, pp. 56-62, 1999.
[5] F. Gardner, "Charge-Pump Phase-Lock Loops," Communications, IEEE Transactions on, vol. 28, pp. 1849-1858, 1980.
[6] S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation, 1996
[7] B. Miller and B. Conley, "A multiple modulator fractional divider," in Frequency Control., Proceedings of the 44th Annual Symposium on, 1990, pp. 559-568.
[8] T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, "Delta-sigma modulation in fractional-N frequency synthesis," Solid-State Circuits, IEEE Journal of, vol. 28, pp. 553-559, 1993.
[9] G. Chien and P. R. Gray, "A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications," in Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. IEEE International, 2000, pp. 202-203, 458.
[10] R. Aparicio and A. Hajimiri, "A noise-shifting differential Colpitts VCO," Solid-State Circuits, IEEE Journal of, vol. 37, pp. 1728-1736, 2002.
[11] K. Kachun and H. C. Luong, "A 0.35-V 1.46-mW low-phase-noise oscillator with transformer feedback in standard 0.18-μm CMOS process," in Custom Integrated Circuits Conference. Proceedings of the IEEE, 2003, pp. 551-554.
[12] W. Andress and H. Donhee, "Standing wave oscillators utilizing wave-adaptive tapered transmission lines," in VLSI Circuits. Digest of Technical Papers. Symposium on, 2004, pp. 50-53.
[13] A. Hajimiri and T. H. Lee, "Design issues in CMOS differential LC osci llators," Solid-State Circuits, IEEE Journal of, vol. 34, pp. 717-724, 1999.
[14] T. K. K. Tsang and M. N. El-Gamal, "A high figure of merit and area-efficient low-voltage (0.7-1 V) 12 GHz CMOS VCO," in Radio Frequency Integrated Circuits (RFIC) Symposium, IEEE, 2003, pp. 89-92.
[15] D. B. Leeson, "A simple model of feedback oscillator noise spectrum," Proceedings of the IEEE, vol. 54, pp. 329-330, 1966.
[16] A. Hajimiri and T. H. Lee, "A general theory of phase noise in electrical oscillators," Solid-State Circuits, IEEE Journal of, vol. 33, pp. 179-194, 1998.
[17] B. Razazvi, RF Microelectronics. New York: Prentice Hall, 1998.
[18] B. Razavi, Design of Analog CMOS Integrated Circuits: McGraw-Hill 2001.
[19] M. G. Johnson and E. L. Hudson, "A variable delay line PLL for CPU-coprocessor synchronization," Solid-State Circuits, IEEE Journal of, vol. 23, pp. 1218-1223, 1988.
[20] P. Larsson, "A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability," Solid-State Circuits, IEEE Journal of, vol. 34, pp. 1951-1960, 1999.
[21] C. B. Sia, K. W. Chan, C. Q. Geng, W. Yang, K. S. Yeo, M. A. Do, J. G. Ma, S. Chu, and K. W. Chew, "An accurate and scalable differential inductor design kit [RFIC applications]," in Microelectronic Test Structures. Proceedings. ICMTS '04. The International Conference on, 2004, pp. 63-68.
[22] Y. Dong-Jun and K. K. O, "A 14-GHz 256/257 dual-modulus prescaler with secondary feedback and its application to a monolithic CMOS 10.4-GHz phase-locked loop," Microwave Theory and Techniques, IEEE Transactions on, vol. 52, pp. 461-468, 2004.
[23] M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K. Okabe, A. Ono, and H. Yamada, "A GHz MOS adaptive pipeline technique using MOS current-mode logic," Solid-State Circuits, IEEE Journal of, vol. 31, pp. 784-791, 1996.
[24] J. Yuan and C. Svensson, "High-speed CMOS circuit technique," Solid-State Circuits, IEEE Journal of, vol. 24, pp. 62-70, 1989.
[25] H. Qiuting and R. Rogenmoser, "Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks," Solid-State Circuits, IEEE Journal of, vol. 31, pp. 456-465, 1996.
[26] M. Tiebout, C. Sandner, H. D. Wohlmuth, N. Da Dalt, and E. Thaller, "A fully integrated 13 GHz Delta-Sigma; fractional-n PLL in 0.13 um CMOS," in Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. IEEE International, 2004, pp. 386-534 Vol.1.
[27] L. Yu-Jen and L. Tsung-Hsien, "A 10-GHz CMOS PLL with an Agile VCO Calibration," in Asian Solid-State Circuits Conference, 2005, pp. 213-216.

簡易檢索 / 詳目顯示

相關論文