在RF射頻收發機中，PLL的特性非常重要，PLL內部包含了相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、壓控振盪器(VCO)、除頻器(FD)，而為了追求低功耗，低相位雜訊，與較寬的除頻範圍，在這其中又以壓控振盪器和注入鎖定除頻器特性最重要，而本論文主要研製鎖相迴路之注入鎖定除頻器。

首先，第一部分我們呈現一個寬頻除二注入鎖定除頻器，此除頻器使用台積電矽鍺0.18 μm製程，晶片面積為0.859 × 0.817 mm2。此除二除頻器設計基於一電容耦合的壓控振盪器，且利用電阻加入共振腔來增加除頻範圍。此除頻器最佳工作電壓操作在0.8伏特，整體功耗為6.23 mW，在注入強度為0 dbm時，除頻範圍可從3.1 GHz ~ 9.3 GHz，百分比為100 %。

接著，第二部分呈現一個使用電容性交叉耦合對的注入鎖定除二除頻器，此除頻器使用台積電矽鍺0.18 μm製程，晶片面積為0.884 × 0.645 mm2。此除二除頻器設計基於兩個N型金氧半電晶體交錯耦合對為中心所組成的電壓壓控振盪器，以及一組差動用來注入訊號的N型金氧半電晶體並聯共振腔三個電感所組成。此除二除頻器，在供應電壓為1.09伏特時，消耗為6.3 mW，在注入強度為0dbm時，除頻範圍可從3.8 GH~ 6.8 GHz，百分比為77.55 %。

最後，一個使用電容性交叉耦合對的寬頻除五注入鎖定除頻器，同樣使用台積電0.18 μm製程來實現。此除頻器使用降低品質因素的共振腔來增加鎖頻範圍。此除五除頻器，在供應電壓為0.9伏特時，消耗為2.98 mW，在注入強度為0dbm時，除頻範圍可從9.4 GH~ 12.6 GHz，百分比為29.06 %。

In the RF transceiver, PLL are very important, PLL characteristics include Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF),Voltage Controlled Oscillator (VCO), and Frequency Divider (FD), In order to pursue low-power, low phase noise, wide Locking range, the most important characteristics of performance are VCO and Divider. This thesis presents the design of Injection-Locked Frequency Dividers (ILFDs).

First, a wide locking range divide-by-2 injection-locked frequency divider (ILFD) using a standard 0.18 μm BiCMOS process is presented. The ILFD circuit bases on capacitive cross-coupled oscillator and uses resonator with resistor to enhance the locking range. The power consumption of the ILFD core is 6.72 mW and the locking range is from 3.1 to 9.3 GHz (100 %) at injection power Pinj = 0 dBm. At the supply voltage of 1.09 V, the divider’s free-running frequency is 3.53 GHz. The die area is 0.859 × 0.817 mm2 .

Secondly, this thesis presents a low power and wide locking range divider by-2 injection-locked frequency divider (ILFD) using a standard 0.18 μm BiCMOS process is presented. The ILFD is based on a differential VCO with dual injection MOSFETs for coupling the external signal to the resonator. The power consumption of the ILFD core is 6.3 mW and the locking range is from 3.0 ~ 6.8 GHz (77.55 %) at injection power Pinj = 0 dBm. At the supply voltage of 1.09 V, the divider’s free-running frequency is 2.19 GHz. The die area is 0.884 × 0.645 mm2 .

Finally, a wide-locking range ÷5 ILFD with capacitive cross-coupled oscillator was implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-5 ILFD is used in the resonator to degrade the quality factor so that locking range is enhanced. The power consumption of the ILFD core is 2.98 mW and the locking range is from 9.4 ~ 12.6 GHz (29.06 %) at injection power Pinj = 0 dBm. At the supply voltage of 0.9 V, the divider’s free-running frequency is 1.89 GHz. The die area is 0.987 × 1.096 mm2.

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