本研究旨在探討乾式以及濕式蝕刻對於VCSEL共振腔端面的影響。透過兩種商用矽基板磊晶生長的氮化鎵LED晶圓，我們成功研製出了改善共振腔端面粗糙度的方法，使用KOH和UVO製程，成功將共振腔端面的表面顆粒尺寸從8.25×10 μm改善至0.33×0.33 μm。
這種端面處理的製程方式不僅適用於GaN-on-Si晶圓，還可應用於其他基板的氮化鎵晶圓，例如藍寶石、氮化鎵和碳化矽，只要能去除基板，就可以使用這種方法改善端面平坦度，並控制VCSEL共振腔長度。
此外，針對材料不同極化方向導致無法使用KOH蝕刻的晶圓，我們研究了ICP-RIE蝕刻和UVO方式，以改善表面平坦度並控制共振腔長度。結果顯示，通過這些製程方法，我們成功將表面顆粒尺寸從3.96×2.94 μm改善至0.56×0.61 μm。
綜上所述，本研究展示了改善VCSEL共振腔端面平坦度的製程方法。這項研究有助於提高VCSEL的性能和可靠性，並在光通訊和光學應用等領域具有重要的應用潛力。

The aim of this study was to investigate the impact of dry and wet etching on the resonator facets of VCSELs. Using two commercially available GaN-on-Si LED wafers, we successfully developed methods to improve the roughness of the resonator facet by employing KOH and UVO processes, which reduced the surface particle size from 8.25×10 μm to 0.33×0.33 μm. It is worth noting that this facet improvement process is not limited to GaN-on-Si wafers but can also be applied to other GaN wafers grown on different substrates such as sapphire, GaN, and SiC, as long as the substrate can be removed. This method allows for improved facet flatness and control of the VCSEL resonator length.
Furthermore, for wafers where the use of KOH etching was not feasible due to material polarization, we investigated ICP-RIE etching and UVO processes to improve surface flatness and control the resonator length. The results showed that these processing methods successfully reduced the surface particle size from 3.96×2.94 μm to 0.56×0.61 μm.
In summary, this study demonstrated process methods for improving the flatness of VCSEL resonator facets. This research contributes to enhancing the performance and reliability of VCSELs and holds significant potential for applications in optical communications and optical systems.

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