本論文研製一高頻化錯相式降壓型功率因數修正器。高頻操作的主要目的是減少電路所需電感量和體積，錯相式架構的電感器採用整合電感器，並且利用電路板上的佈局當作電感器繞組，以減少電感體積和成本，降壓型架構則可降低輸出電容之耐壓規格。由於操作頻率的增加，切換損失也因此隨之增加，所以本論文採用GaN FET，使得因為高頻化所增加之切換損失降至最低。本論文透過模擬軟體PSIM驗證控制電路、模擬軟體Simplis進行損耗分析。最後設計並實作一300 W高頻化錯相式降壓型功率因數修正器，其輸出規格為80 V/3.75 A，輸入範圍則是90 VAC~264 VAC，切換頻率為300 kHz，滿載效率最高可達95.21 %，總諧波失真符合IEC 61000-3 -2 Class D規範。

The main purpose of this thesis is to study and implement an interleaved buck power factor corrector (PFC) with high-frequency operation. High-frequency operation can reduce the inductor size and the converter’s volume. The inductors for the interleaved topology are integrated into one inductor. Additionally, the traces on the PCB are treated as windings to further reduce the cost and volume. With the buck-type topology, the voltage rating for the output capacitor is lower. High switching frequency will result in higher switching loss. Therefore, GaN-based FETs are selected as the main switches to reduce the switching loss. In this thesis, simulations of controller and loss analysis are performed by PSIM and Simplis, respectively. Finally, a 300-W interleaved buck PFC prototype with an output of 80 V/3.75 A and a fixed switching frequency of 300 kHz was built to verify the operations of the circuit and theoretical analysis. The efficiency of the tested prototype reaches 95.21 % at full load. And the line current harmonic contents can also meet the IEC 61000-3-2 Class D regulations.

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