快閃記憶體具有可擴充、低功耗、高效能等優點，使其廣泛地存在於消費性電子產品中；隨著製程演進，不斷增加的資料密度使儲存資料的雜訊容忍範圍縮小，導致快閃記憶體的良率與可靠度下降。因此，我們需要探討更加高效率的快閃記憶體修復技術。
常見的快閃記憶體修復技術中，粗粒度內建自我修復技術用於修復永久性故障，而錯誤更正碼則廣泛地用於更正暫時性故障，而這些修復技術的缺點分別是大粒度備用資源造成得修復效率差以及統一的更正能力帶來的成本問題。為了解決這些問題，本篇論文提出整合性漸進式內建自我修復技術。首先，我們提出 March-CFT 測試演算法，使得更多的故障模型可以被測試，其中包含讀取干擾故障與故障的可通過性，並根據故障字典診斷故障類型。
整合性漸進式內建自我修復 (Integrated Progressive Built-In Self-Repair, IPBISR) 技術在製造測試階段使用錯誤更正碼修復故障單元，而無法被錯誤更正碼修正的故障再由細粒度內建自我修復技術修復。我們以漸進式錯誤更正碼取代傳統具有單一更正能力的錯誤更正碼，根據故障分佈情形，逐步提高快閃記憶體的ECC保護能力。
我們以模擬器對提出的整合性漸進式內建自我修復技術進行評估，實驗結果顯示，良率與可靠度獲得大幅度的提升，且所需的硬體成本可以忽略不計。在故障注入比例為可通過故障95 %、不可通過故障5 % 的1 GB快閃記憶體中，修復率可以達到100 %，且在運作106小時以後仍具有100 % 的可靠度。

Flash memory has the advantages of good scalability, low-power consumption, and high performance. It is widely used in consumer electronic products. As the process technologies keep progressing, the ever increasing data density shrinks the noise tolerance ranges of the stored data. This will further threat the yield and reliability of flash memory. It is inevitable to seek for efficient and effective techniques for raising yield and reliability of flash memory.
Conventional coarse-grained built-in self-repair (CGBISR) techniques and error correction codes (ECC) are widely used for repairing permanent faults and transient faults, respectively. The main drawbacks of these techniques include the large granularity of spare usage and the uniform ECC protection capabilities. To cure these dilemmas, we propose integrated progressive BISR (IPBISR) techniques in this thesis. We first propose March-CFT test algorithm, which can cover more fault models such as read disturb faults and determine the passability of the detected faults. Dictionary-based diagnosis techniques are also presented for diagnosing the detected faults.
IPBISR uses ECC to repair faulty cells during the manufacturing test stage. The remaining faults are then subject to the repair capabilities of the fine-grained built-in self-repair (FGBISR). Instead of the uniform protection for conventional ECC techniques, IPBISR can also progressively increases the protection capabilities of ECC based on the fault distributions of flash memory in the field.
A simulator is implemented for evaluating the novelties of the proposed IPBISR techniques. Experimental results show that reliability and yield can be enhanced greatly with negligible hardware overhead. For a 1 GB flash memory with 95 % passable faults and 5 % unpassable faults injected, we can achieve nearly 100% repair rate. Moreover, after 106 operation hours, the reliability can be remained at 100%.

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