近年來消費性電子產品如手機、固態硬碟、數位相機等迅速地發展，對於儲存裝置的容量需求也日益增加。其中快閃記憶體具有存取時間短、高儲存密度和低功率消耗等優點，使得快閃記憶體被廣泛應用於這些產品的儲存裝置。快閃記憶體是一種由浮閘電晶體所組成的非揮發性記憶體，快閃記憶體藉由將電子儲存於浮閘上或將浮閘內部所儲存的電子移除來完成寫入或清除動作。然而隨著半導體製程的縮減，快閃記憶體在良率、可靠度和耐久度上也面臨到嚴重的議題。而最常被使用來解決這些議題的方法為使用錯誤更正碼技術。錯誤更正碼技術可以修復快閃記憶體的永久性故障細胞進而增加記憶體使用的耐久度，藉此改善快閃記憶體的製造良率與可靠度。然而當一個編碼字的故障位元數量超過使用的錯誤更正碼技術的修復能力範圍時，這個編碼字就無法被正確地修復。
因此，本篇論文提出基於故障知曉之適應性乘積架構錯誤更正碼技術來解決這些問題，主要想法為使用在非及型快閃記憶體的頁緩衝器中適應性地改變錯誤更正碼編碼字的組成位元在快閃記憶體內的儲存位置，使得快閃記憶體在進行寫入與讀取動作時，故障細胞能均勻地分散到不同的編碼字中。根據在產品測試或線上內建自我測試的結果，可以得知快閃記憶體每一個快閃頁的故障細胞分佈，並藉由執行故障分散演算法以評估位移資訊。
根據實驗的結果，當快閃記憶體中有故障發生時，相較於只使用乘積碼技術，使用本篇技術可以更進一步地改善記憶體的修復率。另外在可靠度方面，結合了本篇技術的乘積碼技術，在正常操作下經過 800,000 小時後，快閃記憶體的可靠度仍然可以維持在 99% 的水準。

In recent years, the development of consumer products such as mobile devices, digital cameras, and solid-state disks (SSD) keeps growing rapidly. As a result, the demand of the storage devices gets increased. On the other hand, flash memory is widely used as the storage devices of these products due to its high storage density, low power consumption, and short access time. Flash memory is an electronic non-volatile computer storage device which consists of floating-gate transistor arrays. It stores electric charges or removes charges on the floating gate to electrically program or erase stored data, respectively. However, the reduced operational margins, reliability, and endurance have been considered as the main issues for the flash memory. Error correction code (ECC) is the most effective fault-tolerant technique to overcome such problems. ECC can correct faulty bits of the memory data and further increase the endurance. Nevertheless, the protection of ECC fails when the number of faulty bits in any codeword is higher than its correction capability. Obviously, reliability and endurance are crucial problems for flash memory.
In this thesis, we propose the fault-aware product code scheme to improve the endurance and reliability of flash memory. The proposed scheme adaptively adjusts the constituent cells in the page buffer for each codeword before storing into the flash page. The multiple faulty bits within any codeword then can be evenly distributed over all codewords during the memory read operations. The proposed scheme takes advantage of the built-in self-test and on-line testing procedures to get the fault information of each flash page. According to the fault information, the proposed scheme can evaluate the shift count for each codeword by the fault scrambling algorithm.
Experimental results show that the proposed scheme can achieve higher repair rates as compared with the original product code scheme. Furthermore, the flash memory can still have 99% reliability after 800,000 operation hours. It is evident that the proposed scheme can extend the life time of the flash memory significantly.

[1] Semico Res. Corp., Phoenix, AZ, USA, ASIC IP Rep., 2007. [Online]. Available: http://www.semico.com/content/semico-systemschip-%E2%80%93-braver-new-world
[2] S. Aritome, and T. Kikkawa“ Scaling challenge of self-aligned STI cell (SA-STI cell) for NAND flash memories,” Solid-State Electronics, vol. 82, pp. 54-62, Feb. 2013
[3] R. Micheloni, M. Picca, S. Amato, H. Schwalm, M. Scheppler, and S. Commodaro. “Non-volatile memories for removable media,” Proc. IEEE, vol. 97, no. 1, pp. 148-160, Jan. 2009.
[4] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to flash memory,” Proc. IEEE, vol. 91, no. 4, pp. 489-502, Apr. 2003.
[5] R. C. Baumann, “Soft errors in advanced semiconductor devices—part I: The three radiation sources,” IEEE Trans. Device and Materials Reliability, vol. 1, no. 1, pp. 17-22, Mar. 2001.
[6] W. Kuo, W. T. K. Chien, and T. Kim, “Reliability, yield, and stress burn-in,” Kluwer Academic Publishers, Boston, 1998.
[7] J. C. Yeh, K. L. Cheng, Y. F. Chou, and C. W. Wu, “Flash memory testing and built-in self-diagnosis with march-like test algorithms,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 6, pp. 1101-1113, June 2007.
[8] N. Mielke, T. Marquart, N. Wu, J. Kessenich, H. Belgal, E. Schares, F. Trivedi, E. Goodness, and L. R. Nevill, “Bit error rate in NAND flash memories,” in Proc. IEEE International Reliability Physics Symp. (IRPS), pp. 9-19, July 2008.
[9] Y. Y. Hsiao, C. H. Chen, and C. W. Wu, “A built-in self-repair scheme for NOR-type flash memory,” in Proc. IEEE VLSI Test Symp. (VTS), Berkeley, pp. 114-119, Apr. 2006.
[10] Y. Y. Hsiao, C. H. Chen, and C. W. Wu, “Built-in self-repair schemes for flash memory,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 8, pp. 1243-1256, Aug. 2010.
[11] O. Ginez, J. M. Portal, and H. Aziza, “An on-line testing scheme for repairing purposes in flash memories,” in Proc. IEEE Int’l Symp. Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp. 120-123, Apr. 2009.
[12] O. Ginez, J. M. Portal, and H. Aziza, “Reliability issues in flash memories: an on-line diagnosis and repair scheme for word line drivers,” in Proc. Int’l Workshop on Mixed-Signals, Sensors, and Systems Test, pp. 1-6, June 2008.
[13] C. Argyrides, D. K. Pradhan, and T. Kocak, “Matrix codes for reliable and cost efficient memory chips,” IEEE Trans. VLSI Systems, vol. 19, no. 3, pp. 420-428, Mar. 2011.
[14] S. Tanakamaru, C. Hung, and K. Takeuchi, “Highly reliable and low power SSD using asymmetric coding and stripe bitline-pattern elimination programming,” IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 85-96, Jan. 2012.
[15] T. H. Chen, Y. Y. Hsiao, Y. T. Hsing, and C. W. Wu, “An adaptive-rate error correction scheme for NAND flash memory,” in Proc. IEEE VLSI Test Symp. (VTS), pp. 53-58, June 2009.
[16] C. G. Yang, Y. Emre, and C. Chakrabarti, “Product code schemes for error correction in MLC NAND flash memories,” IEEE Trans. VLSI Systems, vol. 20, no. 12, pp. 2302-2314, Dec. 2012.
[17] R. Motwani, Z. Kwok, and S. Nelson, “Low density parity check (LDPC) codes and the need for stronger ECC,” in Flash Memory Summit, 2011 [Online]. Available: http://www.flashmemorysummit.com/
[18] S. Tanakamaru, Y. Yanagihara, and K. Takeuchi, “Error prediction LDPC and error recovery schemes for highly reliable Solid-State Drives (SSDs),” IEEE J. Solid-State Circuits, vol. 48, no. 11, pp. 1-14, Nov. 2013.
[19] S. Lin and D. J. Costello, Error control coding, 2nd ed., Englewood Cliffs, NJ: Pearson Prentice Hall, 2014.
[20] G. Forney, “On decoding BCH codes,” IEEE Trans. on Information Theory, vol. 11, no. 4, pp. 549-557, Oct. 1965.
[21] R. F. Huang, J. F. Li, J. C. Yeh, and C. W. Wu, “A simulator for evaluating redundancy analysis algorithm of repairable embedded memories,” IEEE International On-Line Testing Workshop (IOLTW), pp. 262-267, July 2002.
[22] T. S. Chung, D. J. Park, S. Park, D. H. Lee, S. W. Lee, and H. J. Song, “A survey of flash translation layer,” Journal of Systems Architecture, vol. 55, no. 5-6, pp. 332-343, May 2009.
[23] A. Ban, “Flash File System,” US Patent No. 5,404,485, 1995.
[24] J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho, “A space-efficient flash translation layer for compact flash systems,” IEEE Trans. Consumer Electronics, vol. 48, no. 2, pp. 366-375, May 2002.
[25] R. Subramani, H. Swapnil, N. Thakur, B. Radhakrishnan, and K. Puttaiah, “Garbage collection algorithms for NAND flash memory devices -- An overview,” in Proc. Modeling Symp. (EMS), pp. 81-86, Nov. 2013.
[26] M. C. Yang, Y. M. Chang, C. W. Taso, P. C. Huang, Y. H. Chang, and T. W. Kuo, “Garbage collection and wear leveling for flash memory: past and future,” in Proc. Int’l Conf. Smart Computing (SMARTCOMP), pp. 66-73, Nov. 2014.
[27] C. T. Huang, J. R. Huang, C. F. Wu, C. W. Wu, and T. Y. Chang, “A programmable BIST core for embedded DRAM,” IEEE Design & Test of Computers, vol. 16, no. 1, pp. 59-70, Jan.-Mar. 1999.
[28] IEEE 1005 standard definitions and characterization of floating gate semiconductor arrays, Piscataway, NJ: IEEE Standards Dept., 1999.
[29] R. W. Hamming, “Error detecting and error correcting codes,” Bell System Tech. J., vol. XXVI, no. 2, pp. 147-160, Apr. 1950.
[30] R. Micheloni, R. Ravasio, A. Marelli, E. Alice, V. Altieri, A. Bovino, L. Crippa, E. Di Martino, L. D’Onofrio, A. Gambardella, E. Grillea, G. Guerra, D. Kim, C. Missiroli, I. Motta, A. Prisco, G. Ragone, M. Romano, M. Sangalli, P. Sauro, M. Scotti, and S. Won, “A 4Gb 2b/cell NAND flash memory with embedded 5b BCH ECC for 36MB/s system read throughput,” in Proc. IEEE Int’1 Solid-State Cir. Conf. (ISSCC), Feb. 2006, pp. 497-506.
[31] W. W.Peterson, “Encoding and error-correction procedures for the Bose-Chaudhuri Codes,” IEEE Trans. Information Theory, vol. 6, no. 4, pp. 459-470, Sep. 1960.
[32] X. Youzhi, “Implementation of Berlekamp-Massey algorithm without inversion,” IEE Proc. Communications, Speech and Vision, vol. 138, no. 3, pp. 138-140, June 1991.
[33] Y. Sugiyama, M. Kasahara, S. Hirasawa, and T. Namekawa, “A method for solving key equation for decoding Goppa codes,” Information and Control 27, pp. 87-99, Jan. 1975.
[34] Y. Chen and K. Parhi, “Small area parallel Chien search architectures for long BCH codes,” IEEE Trans. on VLSI System, vol. 12, no. 5, pp. 545-549, May 2004.
[35] C. H. Stapper, F. M. Armstrong, and K. Saji, “Integrated circuit yield statistics,” Proceedings of the IEEE, vol. 71, no. 4, pp. 453-470, Apr. 1983.