化學機械平坦化(Chemical Mechanical Planarization, CMP)目前已被廣泛應用於IC產業中，隨著近年來半導體線寬不斷縮減，CMP製程之穩定性與重現性不斷面臨挑戰。而在評估拋光墊性能的部分，目前大多單以高度參數或是空間參數定義拋光墊性能狀態，使得拋光墊無法最有效被應用，致使耗材經費高居不下。本研究目的為使用混合參數搭配功能參數來評估拋光墊拋光效率指標(Polishing Efficiency Index, PEI)，針對精拋墊較特殊之表面形貌，定義CMP精拋墊性能狀態。研究方法，於CMP製程前，透過雷射共軛焦量測精拋墊表面形貌，以量測之表面粗度高度參數即均方根高度(Sq)作為假設精拋墊受壓後之乘載作為基準，接著判斷功能參數即粗度波峰高度(Spk)作為拋光墊粗度峰未受壓之高度，再以量測之點資料計算混合參數即介面展開比(Developed interfacial area ratio, Sdr)表示拋光墊受壓後的工作面積百分比，進而推算出拋光墊拋光效率指標(PEI)，最後再由半導體淺溝槽隔離(Shallow Trench Isolation, STI)製程中之CMP製程進行驗證。實驗結果，透過Politex-Hi拋光墊對二氧化矽薄膜晶圓(SiO2)進行九組實驗參數分析，以1.82 psi與80 rpm可取得最佳晶圓表面粗糙度且精拋墊PEI越大，晶圓材料移除率上升，但晶圓表面形貌也較差。研究成果顯示，精拋墊PEI越小，晶圓材料移除率下降，但會取得較佳之晶圓表面形貌。未來於STI CMP製程前，可先透過拋光墊拋光效率指標評估所用之拋光墊性能，以提高製程效能。

Chemical mechanical planarization/polishing (CMP) has been widely adopted in the integrated circuit (IC) fabrication. Due to demand of IC downsizing to nanoscale, CMP process stability and reproducibility continue to face stringent challenges. Polishing pad surface topography is one of the major factors for determination on wafer planarization, which pad polishing efficiency index (PEI) can be considered as one of quantification of pad surface performance in CMP process. This study is to develop PEI based on the interfacial area ratio (Sdr) and related root-mean-square surface roughness(Sq) and (Spk). The PEI is (Sdr) defined by the ratio between multiplication of the interfacial area ratio and reduced peak height (Spk) dividing to the root mean square height (Sq). Finally, the shallow trench isolation (STI) CMP process is used to verified by PEI. The CMP process of silicon oxide (SiO2) and silicon nitride (Si3N4) film wafers has been verified to identify the correlation between the pad PEI and material removal rate (MRR) of oxide and nitride film wafer. Experimental results show that the PEI increases as with MRR of oxide wafer increasing and also as decreasing wafer surface topography. Thus the PEI can be used a pad performance index for STI CMP process based on current configuration of this study. Results of this study can be further adopted as an index for in-situ monitoring of pad topography for process control of STI CMP for advanced node IC demands.

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