快閃記憶體擁有良好的可擴充性、高效能及低成本等特性，加上近年來製程穩定與成熟，快閃記憶體廣泛出現在消費性電子產品中，像是智慧型手機、筆記型電腦與數位影音播放器等等。快閃記憶體儲存資料的值是依靠電子是否儲存於浮閘中來作為依據，隨著製程的進步，多階細胞 (Multiple-Level Cell, MLC)、三階細胞 (Triple-Level Cell, TLC) 及四階細胞 (Quad-Level Cell, QLC) 等技術被提出，由於每個細胞可以儲存 1 個位元以上的資料，快閃記憶體的儲存密度有效上升，但這也使得每個狀態間的雜訊邊界變小，隨著製程的微縮，快閃記憶體的可靠度和耐久度受到嚴重的威脅。為了改善這些問題，錯誤更正碼技術是最為常見的方法來修正快閃記憶體中的錯誤，其中故障可分為永久性故障和干擾性故障兩大類，雖然都可以靠錯誤更正碼技術修復，當編碼字的錯誤數量高於錯誤更正碼的更正能力時，該編碼字就無法被修復。
在這樣的情況下，我們提出一種全面的故障分類，將故障分為存 0 安全故障與存 1 安全故障，並結合故障遮蔽技術將故障遮蔽機率最大化。其主要概念為根據故障特性來儲存資料，以固定型故障來說明，固定於邏輯 0 的故障，在儲存邏輯 1 時會使得資料由邏輯 1 轉變為邏輯 0；而此時儲存邏輯 0 則為安全值。因此，本研究提出適應性資料重映射技術將資料重映射至安全的值中。此外為了減低資料重映射技術的硬體成本，我們採用修正餘度 (Correction Slack) 的概念 [1]，藉由計算錯誤更正碼所剩餘的保護位元數量，針對修正餘度低於或等於使用者自訂的門檻值的資料以資料重映射技術保護。
本研究也實現適應性資料重映射技術的硬體電路，且開發出模擬器對一個 128 MB 快閃記憶體的故障遮蔽效率、修復率、良率、可靠度及硬體成本進行分析。實驗結果顯示本技術可有效提升故障遮蔽機率，快閃記憶體在三時五萬小時使用後可靠度仍保有 98.4%，與傳統錯誤更正碼比較下的修復率也明顯較高。

Flash memory has good device features such as scalability, high performance, low cost, and the fabrication technology is stable and mature recently. It is widely used in consumer electronic products such as smart phones, notebooks, digital audio players, and so on. The data value stored in a flash memory cell depends on the number of charges contained in the floating gate. Owing to the rapid progress of the process technologies, the multi-level cell (MLC), triple-level cell (TLC), and the quad-level cell (QLC) techniques are developed. Flash memory density increases rapidly since each cell can store more than one bit. However, the noise margin of each state becomes narrower. As the process scaling keeps shrinking, the reliability and endurance of flash memories are seriously threatened. To cure this problem, the most popularly used technique is the error correction code (ECC) which can correct error bits in flash memory. In general, permanent faults and disturb faults are the main fault types of flash memories, both can be repaired by ECC. However, when the number of erroneous bits is more than the correction capability of the adopted ECC, codewords cannot be repaired correctly.
To cure this dilemma, we propose a comprehensive fault classification method based on the 1-safe and the 0-safe fault types. Thereafter, a novel fault masking technique is presented to maximize the masking probability. The main idea is that the data bits stored in the faulty cells are based on their fault behaviors. For example, the faulty cell with a stuck-at 0 fault cannot store logic 1 since the fault will be activated. Alternately, logic 0 is a safe value for this faulty cell. Therefore, the adaptive data remapping (DR) technique is proposed to remap data to their safe values for faulty cells. Besides, in order to reduce the hardware cost of the proposed DR technique, we adopt the concept of correction slack, which represents the remaining correction capability of the adopted ECC. Data words are equipped with the DR technique when the correction slack is less than or equal to the user-defined threshold.
The corresponding hardware architecture of the adaptive DR technique is also proposed in this paper. A simulator is developed to analyze the fault masking efficiency, repair rate, yield, reliability, and hardware overhead for a 128-MB flash memory equipped with the adaptive DR technique. Experimental results show that the proposed technique can effectively increase the fault masking probability. The flash memory can still have 98.8% reliability after 900,000 operation hours. The repair rate is also higher as compared to the traditional ECC scheme.

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