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研究生: 楊文凱
Wen-Kai Yang
論文名稱: 針對快閃記憶體之可適應調整主記憶體的緩衝區設計
An Adaptive Host Memory Buffer Design for DRAM-less Flash Memory
指導教授: 吳晋賢
Chin-Hsien Wu
口試委員: 吳晋賢
Chin-Hsien Wu
陳雅淑
Ya-shu Chen
謝仁偉
Jen-Wei Hsieh
林昌鴻
Chang-Hong Lin
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2017
畢業學年度: 105
語文別: 中文
論文頁數: 46
中文關鍵詞: 快閃記憶體主記憶體的緩衝區固態硬碟快閃記憶體轉換層
外文關鍵詞: Host Memory Buffer, Flash Memory, Solid State Disk, Flash Translation Layer
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  • 近年來固態硬碟(Solid State Disk) 發展越來越成熟,不管是讀寫速度、體積、抗震程度和功耗都優於一般硬碟(Hard Disk Drive),固態硬碟目前的缺點為成本與一般硬碟相較之下高出許多。為了降低成本近年來出現了DRAM-less的固態硬碟,也就是把原本固態硬碟中的DRAM去除,只要將固態硬碟中的DRAM去除就可以達到節省成本的目的,將每顆SSD的價格壓縮。但是DRAM原本在固態硬碟中作為Cache使用,因此移除Cache之後效能必定會大大的降低,為了解決這問題Host Memory Buffer被提了出來,在Host端做出了一個Memory Buffer統一管理下面所有的DRAM-less 固態硬碟,這樣可以大大的提升它們的效能。本篇論文題出了一個有效管理 Host Memory Buffer的方法,依據Ghost Caching 機制來有效的分配 Cache中每顆SSD所分配到的資料緩衝區(Data Buffer)及映射緩衝區(Mapping Buffer)空間,達到提升Cache的命中率以及增加SSD效能的目的。


    In recent years, the development of solid-state drives (SSDs) is mature because the read and write speed, volume, shock resistance and power consumption are better than hard-disk drives (HDDs). However, the current shortcoming of SSDs is the price that is more expensive than HDDs. In order to reduce the cost of SSDs, DRAM-less SSDs have been proposed. If DRAM in SSDs was removed, it can achieve cost savings and cut the price of each SSD. However, DRAM was originally used in SSDs as data cache or mapping cache, the performance of SSDs without DRAM could be greatly reduced. Therefore, the concept of host memory buffer was proposed by reserving memory buffer in the host side to provide DRAM capacity for DRAM-less SSDs to improve the performance. In the thesis, we propose an adaptive host memory buffer design for DRAM-less Flash Memory. Based on the proposed method, the data buffer and mapping buffer can be adjusted effectively and dynamically. We can also increase the hit rate of the data buffer and mapping buffer, and increase the SSD performance.

    目錄 第一章 緒論.....................................1 1.1 前言.....................................1 1.2 論文架構 .................................3 第二章 背景知識與研究動機........................4 2.1 NAND Flash Memory架構.......................4 2.2主機內存緩衝區(Host Memory Buffer).............6 2.3快閃記憶體轉換層(Flash Translation Layer).......7 2.3.1 DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings..8 2.3.2 An Adaptive Partitioning Scheme for DRAM-based Cache in Solid State Drives...............................10 2.3.3 ARC: A self-tuning, low overhead replacement cache....11 第三章 針對可調配主記憶體緩衝區設計...............12 3.1系統架構(System Overview).....................12 3.2主記憶體緩衝區詳細介紹.........................14 3.3 主記憶體緩衝區空間調配........................18 第四章 實驗與效能分析.............................24 4.1 實驗環境.....................................24 4.2實驗流程與結果.................................25 第五章 結論.......................................34 第六章 參考文獻...................................35

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