現今，NAND快閃記憶體憑藉其優越的存取性能和低功耗的特性已經成為主流的儲存媒介。隨著工藝技術的進步，由許多層組成的3D NAND快閃記憶體可以解決平面NAND快閃記憶體所遇到的物理限制。然而，3D NAND快閃記憶體很容易受到工作溫度的影響，導致讀寫錯誤及數據保存錯誤。在本研究中，我們將提出一種透過分散資料的存取以降低溫度對快閃記憶體的影響之方法。此外，還提出了垃圾回收策略，考慮溫度對垃圾回收的影響，避免某些特定快閃記憶體的區塊溫度過度升高。根據實驗結果，我們所提出的方法比最先進的方法可以降低更多的峰值溫度。

Nowadays, NAND flash memory has become a mainstream storage medium due to its superior access performance and low power consumption. With the advancement of the process technology, 3D NAND flash memory (that consists of a lot of layers) can solve the physical limitations encountered by the planar NAND flash memory. However, 3D NAND flash memory is easily affected by the operating temperature and causes cross-temperature and data retention errors. In this study, we will propose a method to reduce the impact of temperature on NAND flash memory by dispersing the heat generated by data access. In addition, a GC strategy is proposed to consider the impact of temperature on the garbage collection (GC) and avoid excessive concentration of temperature rises in certain blocks. According to the experimental results, the proposed method can reduce more peak temperature than the state-of-the-art methods.

[1] S. Karmakar, “Quantum dot gate non-volatile memory as single level cell (slc), multi-level cell (mlc) and triple level cell (tlc),” in 2018 IEEE Long Island Systems, Applications and Technology Conference (LISAT), pp. 1–5, IEEE, 2018.
[2] E.-K. Jang, I.-J. Kim, C. A. Lee, C. Yoon, and J.-S. Lee, “Analysis of residual stresses induced in the confined 3d nand flash memory structure for process optimization,” IEEE Journal of the Electron Devices Society, vol. 10, pp. 104–108, 2022.
[3] X. Li, Z. Huo, L. Jin, Y. Wang, J. Liu, D. Jiang, X. Yang, and M. Liu, “Investiga- tion of charge loss mechanisms in 3d tanos cylindrical junction-less charge trapping memory,” in 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1–3, IEEE, 2014.
[4] P.-Y. Du, H.-T. Lue, Y.-H. Shih, K.-Y. Hsieh, and C.-Y. Lu, “Overview of 3d nand flash and progress of split-page 3d vertical gate (3dvg) nand architecture,” in 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technol- ogy (ICSICT), pp. 1–4, IEEE, 2014.
[5] Micron, Industry-Leading TLC 3D NAND Solutions for Flagship Smartphones, 2016.
[6] D. Resnati, A. Goda, G. Nicosia, C. Miccoli, A. S. Spinelli, and C. M. Compagnoni, “Temperature effects in nand flash memories: A comparison between 2-d and 3-d arrays,” IEEE Electron Device Letters, vol. 38, no. 4, pp. 461–464, 2017.
[7] C. Zambelli, L. Crippa, R. Micheloni, and P. Olivo, “Cross-temperature effects of program and read operations in 2d and 3d nand flash memories,” in 2018 Interna- tional Integrated Reliability Workshop (IIRW), pp. 1–4, IEEE, 2018.
[8] Y. Luo, S. Ghose, Y. Cai, E. F. Haratsch, and O. Mutlu, “Heatwatch: Improving 3d nand flash memory device reliability by exploiting self-recovery and temperature awareness,” in 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp. 504–517, IEEE, 2018.
[9] C. Zambelli, E. Ferro, L. Crippa, R. Micheloni, and P. Olivo, “Dynamic v th tracking for cross-temperature suppression in 3d-tlc nand flash,” in 2019 IEEE International Integrated Reliability Workshop (IIRW), pp. 1–4, IEEE, 2019.
[10] D. Wu, H. You, X. Wang, S. Zhong, and Q. Sun, “Experimental investigation of threshold voltage temperature effect during cross-temperature write–read operations in 3-d nand flash,” IEEE Journal of the Electron Devices Society, vol. 9, pp. 22–26, 2020.
[11] M. C. Morgul, M. N. Sakib, and M. Stan, “Reliable processing in flash with high temperature,” in 2021 IEEE International Integrated Reliability Workshop (IIRW), pp. 1–6, IEEE, 2021.
[12] G. Malavena, M. Giulianini, L. Chiavarone, A. S. Spinelli, and C. M. Compagnoni, “Random telegraph noise intensification after high-temperature phases in 3-d nand flash arrays,” IEEE Electron Device Letters, vol. 43, no. 4, pp. 557–560, 2022.
[13] Y. Kim, B. Tauras, A. Gupta, and B. Urgaonkar, “Flashsim: A simulator for nand flash-based solid-state drives,” in 2009 First International Conference on Advances in System Simulation, pp. 125–131, IEEE, 2009.
[14] A. Sridhar, A. Vincenzi, M. Ruggiero, T. Brunschwiler, and D. Atienza, “3d-ice: Fast compact transient thermal modeling for 3d ics with inter-tier liquid cooling,” in 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 463–470, IEEE, 2010.
[15] A. Fourmigue, G. Beltrame, and G. Nicolescu, “Efficient transient thermal simula- tion of 3d ics with liquid-cooling and through silicon vias,” in 2014 Design, Automa- tion Test in Europe Conference Exhibition (DATE), pp. 1–6, IEEE, 2014.
[16] A. Fourmigue, G. Beltrame, G. Nicolescu, and E. M. Aboulhamid, “A linear-time approach for the transient thermal simulation of liquid-cooled 3d ics,” in Proceed- ings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 197–206, 2011.
[17] A. Gupta, Y. Kim, and B. Urgaonkar, “Dftl: a flash translation layer employing demand-based selective caching of page-level address mappings,” Acm Sigplan No- tices, vol. 44, no. 3, pp. 229–240, 2009.
[18] Y. Wang, M. Zhang, X. Yang, and T. Li, “A thermal-aware physical space realloca- tion for open-channel ssd with 3-d flash memory,” IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol. 38, no. 4, pp. 617–627, 2018.
[19] Y. Wang, J. Huang, J. Yang, and T. Li, “A temperature-aware reliability enhancement strategy for 3-d charge-trap flash memory,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 2, pp. 234–244, 2018.
[20] Y. Wang, J. Tan, R. Mao, and T. Li, “Temperature-aware persistent data management for lsm-tree on 3-d nand flash memory,” IEEE Transactions on Computer-Aided De- sign of Integrated Circuits and Systems, vol. 39, no. 12, pp. 4611–4622, 2020.
[21] Micron, NAND Flash Memory Data Sheet, 2005
[22] J. Lee, Y. Kim, G. M. Shipman, S. Oral, and J. Kim, “Preemptible i/o scheduling of garbage collection for solid state drives,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 2, pp. 247–260, 2013.
[23] S. Wu, Y. Lin, B. Mao, and H. Jiang, “Gcar: Garbage collection aware cache man- agement with improved performance for flash-based ssds,” in Proceedings of the 2016 International Conference on Supercomputing, pp. 1–12, 2016.
[24] W. Choi, M. Jung, M. Kandemir, and C. Das, “Parallelizing garbage collection with i/o to improve flash resource utilization,” in Proceedings of the 27th International Symposium on High-Performance Parallel and Distributed Computing, pp. 243– 254, 2018.
[25] Y. Cai, Y. Luo, E. F. Haratsch, K. Mai, and O. Mutlu, “Data retention in mlc nand flash memory: Characterization, optimization, and recovery,” in 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), pp. 551–563, IEEE, 2015.
[26] K. Mizoguchi, T. Takahashi, S. Aritome, and K. Takeuchi, “Data-retention character- istics comparison of 2d and 3d tlc nand flash memories,” in 2017 IEEE International Memory Workshop (IMW), pp. 1–4, IEEE, 2017.
[27] C. Zhao, L. Jin, D. Li, F. Xu, X. Zou, Y. Zhang, Y. Song, H. Wei, Y. Chen, C. Li, et al., “Investigation of threshold voltage distribution temperature dependence in 3d nand flash,” IEEE Electron Device Letters, vol. 40, no. 2, pp. 204–207, 2018.
[28] J. Coutet, F. Marc, F. Dozolme, R. Guétard, A. Janvresse, P. Lebossé, A. Pastre, and J.-C. Clement, “Influence of temperature of storage, write and read operations on multiple level cells nand flash memories,” Microelectronics Reliability, vol. 88, pp. 61–66, 2018.
[29] L.-P. Chang and T.-W. Kuo, “An adaptive striping architecture for flash memory storage systems of embedded systems,” in Proceedings. Eighth IEEE Real-Time and Embedded Technology and Applications Symposium, pp. 187–196, IEEE, 2002.
[30] M. Wu and W. Zwaenepoel, “envy: a non-volatile, main memory storage system,” ACM SIGOPS Operating Systems Review, vol. 28, no. 5, pp. 86–97, 1994.
[31] A. Kawaguchi, S. Nishioka, and H. Motoda, “A flash-memory based file system.,” in USENIX, pp. 155–164, 1995.
[32] M.-L. Chiang and R.-C. Chang, “Cleaning policies in mobile computers using flash memory,” Journal of Systems and Software, vol. 48, no. 3, pp. 213–231, 1999.
[33] L.-P. Chang, “On efficient wear leveling for large-scale flash-memory storage sys- tems,” in Proceedings of the 2007 ACM symposium on Applied computing, pp. 1126– 1130, 2007.
[34] O. Kwon, K. Koh, J. Lee, and H. Bahn, “Fegc: An efficient garbage collection scheme for flash memory based storage systems,” Journal of Systems and Software, vol. 84, no. 9, pp. 1507–1523, 2011.
[35] S. P. Council, “Spc trace file format specification,” 2002.
[36] D. Narayanan, A. Donnelly, and A. Rowstron, “Write off-loading: Practical power management for enterprise storage,” ACM Transactions on Storage (TOS), vol. 4, no. 3, pp. 1–23, 2008.