本論文提出利用新型相位及頻率誤差補償演算法的全數位式鎖相迴路。首先，我們提出了一個振盪週期對應控制碼呈中解析度的新型數位控制振盪器(DCO)架構，DCO 採用一般常見 LC-tank 架構，在 11 位元之 DCO 控制碼控制下，可提供 2048 個不同的頻率，涵蓋約 5.1175 GHz ~ 6.1248 GHz 之震盪頻率。
相位誤差補償機制，是利用 DCO 為取樣信號，來計數參考時脈訊號 Fref 與除頻器之回授訊號 Fback 之間的相位差，藉此修正除頻器除數，以抵銷 Fref 和 Fback 間的相位差。先解決鎖相迴路追鎖頻率時的相位誤差累積問題，而其後每個 Fref 週期，頻率誤差補償機制與相位誤差補償機制將輪流運作。
頻率誤差補償的機制是由相位誤差補償機制拓展出來，同樣利用 DCO 為取樣信號，來計數參考時脈訊號 Fref 與除頻器之回授訊號 Fback 之間的相位差，藉此計算 DCO 控制碼的改變量(∆code)，以達到頻率校正之目的。
相位頻率誤差補償機制應用在全數位式鎖相迴路的追鎖過程，待系統鎖定後再藉由鎖小 DCO 控制碼的改變量，以增進鎖定後頻率的穩定性。
本論文的晶片是採用 TSMC 0.18 um 1P6M CMOS 製程來實現，除了中解析度的數位控制振盪器、Buffer、除頻器、DTS、PFD 等電路採用 Full-Custom 設計流程實現外，其餘電路由 Cell-Based 設計流程來完成。系統鎖定之頻段範圍為涵蓋5.48 GHz至5.62 GHz共8個頻道，參考時脈為5 MHz。DCO解析度在TT 27℃時平均為 15.7 fs。系統操作功率消耗為 68.02 mW 、晶片面積大約為 1.913 mm2。

關鍵字：全數位式鎖相迴路、相位誤差補償、頻率誤差補償、數位控制振盪器。

This thesis presents a phase-frequency error compensation mechanism for an all digital phase-locked lopp(ADPLL). First a novel digital-controlled oscillator(DCO) was designed. Eleven pairs of symmetrical PMOS varactors are connected in parallel in the tank circuit. The DCO’s output frequency range is from 5.1175 GHz ~ 6.1248 GHz.
The phase error compensation mechanism changes the divisor of the divider to resolve the problem of phase error accumulation by calculating the cycle time difference between the positive edge of the reference clock and the positive edge of the feedback signal from the DCO. After that, The frequency error compensation mechanism is activated to generate the correcting amount of the control-code to fix the frequency error. Next, the phased-frequency error compensation mechanism is used in the acquisition mode of the ADPLL. In the tracking mode, after the system is locked, the DCO control code step is reduced to enhance the frequency stability.
The proposed ADPLL chip was fabricated in TSMC 0.18um 1P6M CMOS process. The DCO, Buffer, Divider, DTS and PFD were implemented by the full-custom design flow. The other part of the ADPLL is realized by the cell-based design flow. The ADPLL frequency range is from 5.48 GHz to 5.62 GHz and its average resolution is 15.7 fs at TT 27℃. The power consumption is 68.02 mW, and the chip size is around 1.913 mm2.

Keywords：all-digital phase-locked loop, phase error compensation, frequency error compensation, digitally controlled oscillator.

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