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研究生: 余柏毅
Bo-Yi Yu
論文名稱: 基於深度學習架構之光學鄰近修正與次級解析輔助特徵圖案擺置
A Deep Learning Framework for Comprehensive Mask Optimization with SRAF Insertion and Edge-based OPC
指導教授: 方劭云
Shao-Yun Fang
口試委員: 郭鴻飛
Hung-Fei Kuo
劉一宇
Yi-Yu Liu
呂學坤
Shyue-Kung Lu
李毅郎
Yih-Lang Li
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2018
畢業學年度: 106
語文別: 英文
論文頁數: 55
中文關鍵詞: 深度學習微影製程次級解析輔助特徵圖案擺置光學鄰近修正(OPC)
外文關鍵詞: Deep Learning, Lithography, Sub- resolution assist feature (SRAF) Insertion, Optical proximity correction (OPC)
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  • 隨著現代積體電路的複雜度不斷增加與製程節點的演進,電路可製造性在現代微影(Lithography)製程中正遭遇許多困難。次級解析輔助特徵圖案(SRAF) 擺置與光學鄰近修正(OPC)等重要的解析度增強技術被應用在最大化製程視窗(Process Window)與加強特徵解析度。目前工業應用中,大量應用了傳統以模型為基礎(Model-Based)的次級解析輔助特徵圖案擺置與光學鄰近修正技術,但也蒙受由迭代最佳化
    過程(Iterative optimization process)所引起的過久的執行時間之缺點。在本論文中,我們提出了第一篇基於深度學習(Deep Learning)架構,同時考慮次級解析輔助特徵圖案擺置與以邊為基礎(Edge-Based)的光學鄰近修正。此外,為了使最佳化的光罩(Optimized Mask)在實際工業應用更加可靠與更有公信力,我們採用了商用微影工具軟體,在晶圓影像(Wafer Image) 上驗證了許多微影度量(Lithographic Metric)。本論文所提出的架構展在實驗結果所呈現的效用與效率,展現了以機器學
    習之顯影最佳化技術在現代複雜與大規模積體電路的成功。


    With the dramatically increase of design complexity and the advance of semiconductor technology nodes, huge difficulties appear during design for manufacturability with existing lithography solutions. Sub-resolution assist feature (SRAF) insertion and optical proximity correction (OPC) are both inevitable resolution enhancement techniques (RET) to maximize process window and ensure feature printability. Conventional model-based SRAF insertion and OPC methods are widely applied in industrial application but suffer from the extremely long runtime due to iterative optimization process. In this thesis, we propose the first work developing a deep learning framework to simultaneously perform SRAF insertion and edge-based OPC. In addition, to make the optimized masks more reliable and convincing for industrial application, we employ a commercial lithography simulation tool to consider the quality of wafer image with various lithographic metrics. The effectiveness and efficiency of the proposed framework are demonstrated in experimental results, which also show the success of machine learning-based lithography optimization techniques for the current complex and large-scale circuit layouts.

    Abstract vii List of Tables xi List of Figures xii Chapter 1. Introduction 1 1.1 Resolution Enhancement Techniques . . . . . . . . . . . . . . . . . . . . 1 1.2 Related Work . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 5 1.3 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 2. Preliminaries 9 2.1 Standard Mask Optimization Flow . . . . . . . . . . . . . . . . . . . . . 9 2.2 Terminologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 3. Proposed Deep Learning Framework 16 3.1 Brief Introduction to Deep Learning . . . . . . . . . . . . . . . . . . . 16 3.2 Proposed Framework . . . . . . . . . . . . . . . .. . . . . . . . . . . . 18 3.3 Feature Extraction for Data . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 Training Data Preparation . . . . . . . . . . . . . . . . . . . . . . . . 22 Chapter 4. Experimental Results 26 4.1 Environment Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.2 Comparison Between with and without SRAF Insertion on Training Data Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3 Comparison Between with and without SRAF Insertion on Testing Data Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4 Proposed framework on enlarged layout . . . . . . . . . . . . . . . . . . 34 Chapter 5. Conclusions 37 Bibliography 38 Publication List 42

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