本論文探討十二位元之連續漸進式(SAR)類比數位轉換器(ADC)的設計與實現。這個ADC架構主要是以連續漸進式類比數位轉換器為基礎，為了提升取樣的操作速度，搭配使用次階式(Subrange)架構運作。另外，本論文提出新的動態邏輯電路來減少比較器輸出至數位轉換器(DAC)切換開關的延遲時間，可以減少整體ADC的轉換時間。為了滿足十二位元的線性度要求，在數位類比轉換器(DAC)中，使用二元式窗切換技術以及電容交換技術，可以得到更好的線性度。
在台積電的65奈米製程下，我們實現兩個連續漸進式類比數位轉換器。第一個ADC是一個十二位元每秒一億次取樣之連續漸進式類比數位轉換器，其晶片面積是0.048平方毫米。在1.2伏特操作電壓以及100MHz取樣頻率下，功耗是1.8毫瓦。量測到的動態效能，有效位元(ENOB)為9.65 bits；訊噪失真比(SNDR)為59.84 dB；無雜散動態範圍(SFDR)為67.18 dB。在使用電容交換技術之後，無雜散動態範圍(SFDR)提升到80.74dB。靜態效能量測：微分非線性誤差(DNL)為+1.47/-0.72 LSB；積分非線性誤差(INL)為+4.01/-0.7 LSB。第二個ADC是一個十二位元每秒兩億五千萬次取樣之連續漸進式類比數位轉換器，其晶片大小為0.124平方毫米。在1.2伏特的操作電壓及250MHz的取樣頻率下，模擬結果的動態效能為，訊噪失真比(SNDR)為64 dB，無雜散動態範圍(SFDR)為82.7 dB。

This thesis is aimed to present 12-bit Sub-ranged successive approximation register (SAR) analog-to-digital converters (ADCs). In order to speed up the sampling rate, the ADC architecture is proposed using the subrange SAR operation. Besides, by applying a new dynamic latch logic architecture, the DAC control delay between the comparator output and DAC switch is reduced. Thus, the sampling rate of the ADC is also improved. To achieve the 12-bit linearity requirement, the binary-window and capacitor-swapping switching techniques are applied in the DAC.
Two ADCs were implemented in TSMC 65 nm digital CMOS process. The first one is a 12-bit 100-MS/s ADC, which occupies an active area of 0.048 mm^2 . At 100-MS/s, the ADC consumes a total power of 1.8 mW from a 1.2V supply. The measured ENOB is 9.65 bits. Without the capacitor swapping scheme, the measured SNDR and SFDR are 59.84dB and 67.18dB, respectively. After using the swapping scheme, the SFDR is improved to 80.74dB. The measured DNL is+1.47/-0.72 LSB and the INL is +4.01/-0.7 LSB. The other one is a 12-bit 250-MS/s ADC which occupies an active area of 0.124 mm^2 . Using a 1.2V supply and a 250 MHz sampling rate, the measured SNDR and SFDR are 64dB and 82.7dB, respectively.

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