本論文提出一個採用電容校正技術之二十位元每秒十萬次取樣的混合式逐次漸進式類比數位轉換器。對於一個二十位元類比數位轉換器而言，雜訊與線性度分別為兩個主要的設計考量。對於雜訊而言，採用數字斜波類比數位轉換器來抑制比較器所貢獻的雜訊以滿足設計規格。而就著線性度而言，則是使用數位電容校正技術來避免大面積的電容式數位類比轉換器。此外，快速二元視窗切換技術被用來輔助電容校正所需要的部份功能，藉由減少不必要的電容切換，進一步改善無雜散動態範圍。
在台積電的0.18微米CMOS製程下，其晶片面積是6.67平方毫米。在3.3伏特及1.8伏特的操作電壓下，功率消耗為2.48毫瓦。經過電容校正後，在奈奎斯特頻率下，後模擬的訊號對雜訊與失真比是99.5dB，無雜散動態範圍是123.3dB，性能指標是172.6dB。

This thesis presents a 20-bit hybrid successive approximation register analog-to-digital converter (Hybrid-SAR ADC) using capacitor calibration technique. For 20-bit ADCs, noise and linearity are two major design challenges. For the noise, digital slope ADC is proposed to suppress the noise contributed by the comparator to meet specifications. For the linearity, a capacitor calibration technique is proposed to prevent using a large capacitive digital-to-analog converter (C-DAC). In addition, Fast-Binary-Window DAC switching scheme is adopted in this design to assist the proposed capacitor calibration technique and improve the ADC linearity. In addition, spurious free dynamic range (SFDR) is also improved by avoiding unnecessary capacitor switching.
A 20-bit 80-kS/s Hybrid-SAR ADC using capacitor calibration technique is implemented in TSMC 180-nm CMOS. This die area of this ADC is 6.67 mm^2. It consumes 2.48 mW at 3.3 V and 1.8 V supply. After capacitor calibration, at Nyquist, the post-layout simulation results for SNDR and SFDR are 99.5 dB and 123.3 dB, respectively. The simulated figure-of-merit (FOM) is 172.6 dB.

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