類比數位轉換器是非常重要的電路，負責將類比訊號轉換成數位訊號，現今已被廣泛地應用在DSP中對類比訊號的處理，而且是影響系統整體效能的關鍵元件。三角積分調變器與超取樣技術早被應用於現代超大型積體電路設計中的類比數位轉換器。類比數位轉換器有許多種類，而三角積分調變器最大的特色是能將量化雜訊移至高頻端，而且使用低通濾波器濾除，達到一個高解析度的數位訊號。
本論文設計了一個操作於音頻的二階三角積分類比數位轉換器。在傳統的積分器上，運算放大器的差動輸入端有可能因為製程的關係，導致輸入端不對稱，產生偏移電壓，進而造成三角積分調變器的解析度下降。本論文提出一個可以降低偏移電壓對解析度影響的雙重取樣積分器電路，在不增加取樣頻率的情況下，得到兩倍OSR的效果。本論文的三角積分調變器，解析度達到16.19bit，電路使用TSMC 1P6M 0.18m製程設計，晶片面積為0.99 mm2，功率消耗為3.92 mW。

The analog-to-digital converter (ADC) is an important building block in the modern electronic systems. It converts the analog signal into digital form such that it can be processed in a digital signal processing system. There are many different kinds of ADCs. Among them, the ADC that employs the delta-sigma modulator and the oversampling technique pushes the quantization noise to high frequencies and conserves the desired signal at the low frequencies. The quantization noise is therefore easily removed by a low-pass filter. This advantage makes the ADC easily achieve high resolution, especially for audio applications.
In this thesis, I design a second-order ADC for audio applications. The offset voltage of the operational amplifier of my circuit is cancelled by the auto-zeroing technique. A novel double sampling technique is used without increasing the clock rate of the converter. Thus, the oversampling ratio is doubled. The resolution of the proposed ADC is 16.19 bits. The circuit is designed in TSMC 1P6M 0.18um CMOS technology. The chip area is 0.99 mm2 and the estimated power consumption of the proposed ADC is 3.92 mW.

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