應用於無線通訊之連續時間電容式前饋三角積分調變器晶片設計

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研究生：	林彥榕 Yen-Jung Lin
論文名稱：	應用於無線通訊之連續時間電容式前饋三角積分調變器晶片設計 The Continuous-Time Capacitive Feedforward Sigma-Delta Modulators Chip Design for Wireless Communication
指導教授：	黃進芳 Jhin-Fang Huang 劉榮宜 Ron-Yi Liu
口試委員:	黃弘一 none 張勝良 none 徐敬文 none
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2011
畢業學年度：	99
語文別：	英文
論文頁數：	114
中文關鍵詞：	三角積分調變器、抽取濾波器
外文關鍵詞：	Delta-Sigma modulator, decimation filter
相關次數：	點閱：149 下載：6
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由於無線通訊系統的發展，具有數個百萬赫茲頻寬的類比數位轉換器受到大量的需求，三角積分調變器理想上適合這樣的應用。相較於離散時間切換電容電路的實現方式，連續時間三角積分調變器擁有更寬頻的潛力同時也天生具有抗混疊的特性。
在本論文，兩個連續時間三角積分調變器被設計與製作，第一個是應用於WiMAX的四相位帶通三角積分調變器。電容式前饋在這個電路被應用於頻率補償。相較於傳統CIFF架構，電容式前饋是一種簡單的實現方式。時脈為160 MHz的情況下，在一個10MHz的頻寬內這個調變器量測到46 dB的動態範圍，SNDR為37 dB，IM3為-44 dB。在1.8 V的電源下量測的功率消耗是41.5 mW。包含Pads的晶片面積是1.7947 (1.31 x 1.37) mm2。
雖然三角積分調變器能容忍類比電路的不完美特性，但其輸出需要經過抽
取濾波器。另一方面，帶通三角積分調變器的特性不受低頻雜訊的影響，但其輸出需要在數位領域做降轉換。為了示範一個完整的四相位帶通三角積分類比數位轉換器，適用於四相位帶通三角積分調變器的抽取濾波器被設計並模擬。
第二個調變器晶片是一個具有混合主動與被動迴路濾波器的連續時間三角積分調變器，可應用於WCDMA。其中的五階迴路濾波器主要由兩個被動濾波器與三個主動濾波器構成。另外，為了移除一個被用在CIFF架構的加總放大器，電容式前饋架構同樣被使用。區域回授電阻亦使用橋式Ｔ網路來建構以減小佈局面積。使用TSMC 0.18 um 1.8 V CMOS製作後，在2 MHz的頻寬內晶片量測到62 dB的動態範圍，SNDR為60.26 dB，IM3為-48 dB。功率消耗為9 mW。包含pad的總晶片片積為0.642 ( 1.07 x 0.6) mm2。

With increasing development of wireless communication systems, there is a large demand in the wireless communication for analog-to-digital converters (ADCs) that require signal bandwidths of several megahertz. Sigma-delta modulators (ΣΔ modulators) are ideally suitable for such applications. Compared to the discrete-time switched capacitor circuit implementations, continuous-time (CT) ΣΔ modulators have the potentials for wider bandwidth and are also inherent anti-aliasing.
In this thesis, two CT ΣΔ modulators were designed and fabricated. The first one is the complex bandpass ΣΔ modulator for WiMAX application. Capacitive feedforward are employed for frequency compensation. Capacitive feedforward is a simple solution compared to conventional CIFF (chain of integrators with weighted feedforward summation) topology. Clock at 160 MHz, The modulator achieved a measured dynamic range of 46 dB over a 10 MHz signal bandwidth, SNDR of 37 dB, IM3 of -44 dB. The measured power dissipation is 41.5 mW from a 1.8 V supply voltage. Including pads, the chip occupies 1.7947 (1.31 x 1.37) mm2.
Although ΣΔ modulators tolerate to imperfection of analog circuit, the decimation and filtering of the output stream of ΣΔ modulators are necessary. In addition, the performance of bandpass ΣΔ modulators is not interfered by low frequency noise, however, downconversion of the output stream in digital domain is needed. To demonstrate a complete complex bandpass ΣΔ ADC, decimation filter for complex bandpass ΣΔ modulator is designed and simulation results are given.
The second modulator chip is the CT ΣΔ modulator with a hybrid active-passive loop filter for WCDMA application. This 5th-order loop filter architecture mainly consists of two passive integrators and three active integrators. Also, to erase the summation amplifier used in the CIFF topology, the capacitive feedforward structure is also employed. In addition, local feedback resistors are formed as the bridge-T network to reduce the chip area. After chip being fabricated in TSMC 0.18 um 1.8 V CMOS technology, the overall measured results have achieved dynamic range of 62 dB over a 2 MHz signal bandwidth, SNDR of 60.26 dB, IM3 of -48 dB and power dissipation of 9 mW. Including pads, the overall chip area is 0.642 (1.07 x 0.6) mm2

誌謝                                          　
Abstract (in Chinese)
Abstract (in English)
Contents
List of Figures
List of Tables
Chapter 1 Introduction
1 Motivation
2 Organization
Chapter 2 Basic Concepts of Delta Sigma Modulator
1 Introduction
2 Analog to Digital Conversion
3 Delta Sigma Modulation
3.1 Oversampling
3.2 Noise-Shaping ΔΣ ADC
3.3 Multi-Bit ΔΣ Modulator
3.4 Dynamic Element Matching
3.5 Continuous-Time and Discrete-Time Loop Filter
4 Frequency Compensation by Capacitive Feedforward
4.1 Feedback Compensation
4.2 Feedforward Compensation
4.3 Feedforward Compensation by Capacitive Feedforward
5 Performance Metrics
6 Paper Survey
7 Summary
Chapter 3 The Continuous-Time Complex Bandpass Sigma-Delta Modulator Chip Design for WiMAX Application
1 Introduction
2 Complex Bandpass modulator
2.1 Complex Signal
2.2 Complex Filter
2.3 Complex Noise Transfer Function
2.4 Complex ΔΣM Architecture
3 Design of Continuous Time Complex Bandpass Delta Sigma Modulator
3.1 Specification
3.2 Architecture
3.3 Coefficient Design
4 Effects of Non-Idealities on Complex Modulator Performance
4.1 Finite Gain and Finite Bandwidth of Op Amp
4.2 RC Product Variation
4.3 Clock Jitter
4.4 Excess Loop Delay
4.5 DAC Element Mismatch
4.6 Channel Mismatch
5 Circuit Implementation
5.1 3rd Order Complex Filter
5.2 Op Amp
5.3 Quantizer
5.4 Current Steering DACs for Global Feedback
5.5 Current Steering DACs for Local Feedback
5.6 Data Weighted Averaging
5.7 Bandgap Reference
6 Layout Consideration
7 Simulation Results
7.1 Simulation of Output Swing of Op Amp
7.2 Simulation of Non-idealities on Modulator Performance
7.3 Simulation of Output Spectrum and Dynamic Range
8 Measurement Results
7.1 Chip Photograph
7.2 Measurement Setup
7.3 Measurement Results
9 Summary
Chapter 4 Decimation Filter for Complex Bandpass Sigma-Delta Modulator
1 Introduction
2 System Description and Specifications
2.1 DC Offset Correction
2.2 CIC Decimation Filter
2.3 Digital Complex Mixer
2.4 Halfband Filter
3 Circuit Implementation
3.1 Reduction of Hardware Complexity with Truncation
3.2 1-bit Full Adder
3.3 D Flip-Flop
3.4 1-bit Integrator and Differentiator
3.5 Cascaded Integrator and Comb Filter
3.6 12-bit Signed Array Multiplier
3.7 Halfband Filter
4 Simulation Results
5 Summary
Chapter 5 Chip Design of The CT Sigma-Delta Modulator with a Hybrid Active-Passive Loop Filter
1 Introduction
2 Design and Architecture of the Hybrid ΣΔ modulator
3 Effects of Non-Idealities on Hybrid Modulator Performance
3.1 Effect of Non-Ideal Opamp
3.2 RC Product Variation
3.2 Clock Jitter
4 Circuit Implementation
4.1 Op Amp
4.3 Dynamic Comparator and D-latch
4.4 DAC
5 Simulation Results
6 Measurement Results
7 Summary

Chapter 6 Conclusions
1	Thesis Conclusion
2	Future Work
Bibliography
Appendix

                                

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